Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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Endianism<br />
control<br />
SDRC.SDRC_SHARING[14:9]<br />
CSnMUXCFG field<br />
CS1<br />
CS0<br />
Data lane and<br />
endianism control<br />
Interconnect<br />
data[63:48]<br />
Public Version<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong> www.ti.com<br />
<strong>10</strong>.2.4.4.5.2 Endianness-Aware Unpacking<br />
Data transactions can be either big or little endian; the transaction endianness is determined by an<br />
in-band interconnect qualifier. Muxing 64-bit data to 16-/32-bit data is performed according to this qualifier.<br />
For a 64-bit interconnect little-endian write transaction on a 16-/32-bit memory, Data[15(31):0] is written at<br />
the lowest memory address, and Data[63:48(32)] is written at the highest memory address.<br />
For a 64-bit interconnect big-endian write transaction on a 16-/32-bit memory, Data[15(31):0] is written at<br />
the highest memory address, and Data[63:48(32)] is written at the lowest memory address.<br />
Figure <strong>10</strong>-55 shows the data multiplexing scheme.<br />
Figure <strong>10</strong>-55. Data Multiplexing Scheme<br />
Interconnect<br />
data[47:32]<br />
<strong>10</strong>.2.4.4.6 Data Demultiplexing During Read Operations<br />
<strong>10</strong>.2.4.4.6.1 External Bus Combinations<br />
Interconnect<br />
data[31:16]<br />
Config mux and endianism<br />
SDRC data_out[15(31):0]<br />
Data_lane[15(31):0]<br />
Interconnect<br />
data[15:0]<br />
The SDRC pin allocation scenarios are shown in Table <strong>10</strong>-<strong>10</strong>2. These scenarios are defined on a per-CS<br />
basis for maximum flexibility. The pin allocation configurations allow implementation of combinations of<br />
16-/32-bit external interfaces. The data demultiplexer receives 16-/32-bit data from the relevant SDRC<br />
data lane, and then performs a data packing function. The packing function formats the data into 64-, 32-,<br />
16-, or 8-bit format. The data demultiplexer also steers the data from the appropriate data lane. The data<br />
partitioning and data steering are determined by the SDRC.SDRC_SHARING[11:9] CSOMUXCFG and<br />
SDRC.SDRC_SHARING[14:12] CS1MUXCFG bit fields.<br />
Figure <strong>10</strong>-56 shows the data demultiplexing scheme.<br />
2236 <strong>Memory</strong> <strong>Subsystem</strong> SPRUGN4L–May 20<strong>10</strong>–Revised June 2011<br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
sdrc-012