Chapter 10 Memory Subsystem.pdf

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When the memory device does not support native-wrapping burst, there is usually no difference in
behavior between a fixed burst length mode and a continuous burst mode configuration (except for a
potential power increase from a memory-speculative data prefetch in a continuous burst read). However,
even though continuous burst mode is compatible with GPCM behavior, because the GPMC access
engine issues only fixed-length burst and does not benefit from continuous burst mode, it is best to
configure the memory device in fixed-length burst mode.
The memory device maximum-length burst (configured in fixed-length burst wrap or nonwrap mode)
usually corresponds to the memory device data buffer size. Memory devices with a minimum of 16
half-word buffers are the most appropriate (especially with wrap support), but memory devices with
smaller buffer size (4 or 8) are also supported, assuming that the GPMC.GPMC_CONFIG1_i[24:23]
ATTACHEDDEVICEPAGELENGTH field is set accordingly to 4 or 8 words.
The device system issues only requests with addresses or starting addresses for nonwrapping burst
requests; that is, the request size boundary is aligned. In case of an eight-word-wrapping burst, the
wrapping address always occurs on the eight-words boundary. As a consequence, all words requested
must be available from the memory data buffer when the buffer size is equal to or greater than the
ATTACHEDDEVICEPAGELENGTH value. This usually means that data can be read from or written to the
buffer at a constant rate (number of cycles between data) without wait states between data accesses. If
the memory does not behave this way (nonzero wait state burstable memory), wait-pin monitoring must be
enabled to dynamically control data-access completion within the burst beat.
NOTE: When the system burst request length is less than the ATTACHEDDEVICEPAGELENGTH
value, the GPMC proceeds with the required accesses.
10.1.5.3 Timing Setting
The GPMC is a signal generator that offers the maximum flexibility to support various access protocols.
Most of the timing parameters of the protocol access used by the GPMC to communicate with attached
memories or devices are programmable on a chip-select basis. Assertion and deassertion times of control
signals are defined to match the attached memory or device timing specifications and to get maximum
performance during accesses. For example, the timing diagram in Figure 10-7 shows an asynchronous
single-read access performed on an asynchronous device. For more information about GPMC_CLK and
GPMC_FCLK, see Section 10.1.5.3.6.
2110 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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