Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com Below each mapping diagram, a write (encoding) and read (decoding: syndrome generation) sequence is given, with the number of the active buffers at each point in time (yellow). In the inactive zones (grey), no computing is taking place but the data counter is still active. A table on the left summarizes the mode, size0, size1 parameters to program for respectively write and read processing of a page, with the given mapping, where : • P is the size of spare byte section Protected by the ECC (in nibbles) • U is the size of spare byte section Unprotected by the ECC (in nibbles) • E is the size of the ECC itself (in nibbles) • S is the number of Sectors per page (2 in the current diagrams) Each time the processing of a BCH block is complete (ECC calculation for write/encoding, syndrome generation for read/decoding, indicated by red arrows), the update pointer is pulsed. Note that the processing for block 0 can be the first or the last to complete, depending on the NAND page mapping and operation (read or write). All examples show a page size of 1kByte + spares; that is, S = 2 sectors of 512 bytes. The same principles can be extended to larger pages by adding more sectors. The actual BCH codeword size is used during the error location work to restrict the search range: by definition, errors can only happen in the codeword that was actually written to the NAND, and not in the mathematical codeword of n = 2 13 - 1 = 8191 bits. That codeword (higher-order bits) is all-zero and implicit during computations. The actual BCH codeword size depends on the mode, programmed sizes, and sector number (all sizes in nibbles): • Spares mapped and protected per sector (below: see M1-M2-M3-M9-M10): – all sectors: (512) + P + E • Spares pooled and protected by sector 0 (below: see M5-M6): – sector 0 codeword: (512) + P + E – other sectors: (512) + E • Unprotected spares (below: see M4-M7-M8-M11-M12): – all codewords (512) + E 10.1.5.14.3.2.3.1 Per-Sector Spare Mappings In the schemes in Figure 10-33, each 512-byte sector of the main area has its own dedicated section of the spare area. The spare area of each sector is composed of : • ECC, which must be located after the data it protects • Other data, which may or may not be protected by the sector ECC 2158 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
M1 M2 M3 M4 Per-sector spares Spares covered by sector ECC per sector ECC mapping Write Read Write Read Mode Size0 Size1 1 1 P E P+E 0 Per-sector spares Spares covered by sector ECC per sector, left-padded ECC Write Read Write Read Mode Size0 Size1 1 10 1 1 2 2 P 1+E P E Per-sector spares Spares covered by sector ECC ECC not right-aligned Mode Size0 Size1 P E+U P+E U Per-sector spares Spares not covered by ECC ECC right-aligned per sector Mode Size0 Size1 U+E 0 U E Public Version www.ti.com General-Purpose Memory Controller Figure 10-33. NAND Page Mapping and ECC: Per-Sector Schemes 10.1.5.14.3.2.3.2 Pooled Spare Mapping Sector data Sector data Data0 Data1 Prot0 Ecc0 Prot1 Ecc1 512 bytes 512 bytes 0 1 0 1 Sector data Sector data 512 bytes 512 bytes 512 bytes 512 bytes P E U P E U 512 bytes 512 bytes Sector spares Sector spares P E P E 0 size0 size1 size0 size1 0 1 size0 size0 P 1 E P 1 E size0 size1 size0 size1 0 i. 0 1 i. 1 1 inactive 1 inactive Data0 Data1 Prot0 Pad Ecc0 Prot1 Pad Ecc1 0 1 0 1 Sector data Sector data size1 size0 1 U E U E size0 size0 0 1 inactive 0 inactive size1 Data0 Data1 Prot0 Ecc0 U0 Prot1 Ecc1 U1 0 1 0 1 Sector data Sector data 0 inactive 1 inactive size0 size1 size0 size1 0 i. 1 i. size0 s1 size0 s1 Data0 Data1 Unprot0 Ecc0 Unprot1 Ecc1 0 1 Sector spares Sector spares 0 size0 In the schemes in Figure 10-34, the spare area is pooled for the page. • The ECC of each sector is aligned at the end of the spare area. • The non-ECC spare data may or may not be covered by the ECC of sector 0. inactive 1 inactive Sector spares Sector spares Sector spares Sector spares inactive size0 size1 size0 size1 SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 1 gpmc-033 2159
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
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Device SDRAM controller subsystem R
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Public Version www.ti.com SDRAM Con
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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