Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0178 Table 10-143. SMS_POW_CTRL Physical Address 0x6C00 0178 Instance SMS Description This register controls the SMS power management in conjunction with the regular interconnect socket registers. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IDLEDELAY Bits Field Name Description Type Reset 31:8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000 7:0 IDLEDELAY Delay (expressed in L3 clock cycle units) before autoidle, that is, RW 0x80 before disabling the SMS functional clock when no more traffic in the SMS module. SDRAM Controller (SDRC) Subsystem • Module Power Saving: [0] • SMS Register Summary: [1] Table 10-144. Register Call Summary for Register SMS_POW_CTRL Table 10-145. SMS_ROT_CONTROLn Address Offset 0x0000 0180 + (0x0000 0010 * n) Index n = 0 to 11 Physical Address 0x6C00 0180 + (0x0000 0010 * n) Instance SMS Description This register configures the virtual rotated frame buffer module for context #n. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PH PW PS Bits Field Name Description Type Reset 31:11 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000 10:8 PH Exponent based 2 value, 2 ph indicates the page height in bytes for context RW 0x0 #n. 7 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 6:4 PW Exponent based 2 value, 2 pw indicates the page width in bytes for context RW 0x0 #n. 3:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 1:0 PS Exponent based 2 value, 2 ps indicates the pixel size in bytes for context RW 0x0 #n. A value of 3 is invalid. Table 10-146. Register Call Summary for Register SMS_ROT_CONTROLn SDRAM Controller (SDRC) Subsystem • Rotation Engine: [0] [1] • VRFB Context Configuration: [2] [3] [4] • Applicative Use Case and Tips: [5] [6] [7] • SMS Register Summary: [8] 2294Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated RESERVED RESERVED
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-147. SMS_ROT_SIZEn Address Offset 0x0000 0184 + (0x0000 0010 * n) Index n = 0 to 11 Physical Address 0x6C00 0184 + (0x0000 0010 * n) Instance SMS Description This register configures the bank organization for context #n. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED IMAGEHEIGHT RESERVED IMAGEWIDTH Bits Field Name Description Type Reset 31:27 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 26:16 IMAGEHEIGHT Image height in pixels for context #n RW 0x000 15:11 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 10:0 IMAGEWIDTH Image width in pixels for context #n RW 0x000 Table 10-148. Register Call Summary for Register SMS_ROT_SIZEn SDRAM Controller (SDRC) Subsystem • Rotation Engine: [0] [1] [2] • VRFB Context Configuration: [3] [4] • Applicative Use Case and Tips: [5] [6] • SMS Register Summary: [7] Table 10-149. SMS_ROT_PHYSICAL_BAn Address Offset 0x0000 0188 + (0x0000 0010 * n) Index n = 0 to 11 Physical Address 0x6C00 0188 + (0x0000 0010 * n) Instance SMS Description This register allows to configure the physical base address for context #n. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PHYSICALBA Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 30:0 PHYSICALBA Physical base address of the frame buffer for context #n in SDRAM RW 0x00000000 Table 10-150. Register Call Summary for Register SMS_ROT_PHYSICAL_BAn SDRAM Controller (SDRC) Subsystem • Rotation Engine: [0] • VRFB Context Configuration: [1] • Applicative Use Case and Tips: [2] • Physical vs Virtual Address Spaces: [3] • SMS Register Summary: [4] 10.2.8 SDRC Register Manual 10.2.8.1 SDRC Instance Summary Table 10-151 gives some details on the SDRC module instance. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2295
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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