Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0060 Table 10-167. SDRC_DLLA_CTRL Physical Address 0x6D00 0060 Instance SDRC Description This register controls the SDRC DLL A resource used for fine timing tuning on a double-data-rate interface. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIXEDDELAY MODEFIXEDDELAYINITLAT RESERVED Bits Field Name Description Type Reset 31:24 FIXEDDELAY Phase offset value in ModeFixedDelay mode. Maximum RW 0x00 frequency supported in this mode is 83 MHz. FIXEDDELAY steps are defined after DLL cell characterization. 23:16 MODEFIXEDDELAYINITLAT Initial latency before first request to be processed in RW 0x00 ModeFixedDelay mode (1) 0x0: no initial latency before first access 0x1: 2 clock cycles before first access 0x2: 4 clock cycles before first access 0x3: 6 clock cycles before first access 0x4 : 8 clock cycles before first access ... 0xFF: 510 clock cycles before first access 15:8 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x00 7 RESERVED Reserved RW 0x0 6:5 DLLMODEONIDLEREQ Selects the DLL mode upon hardware idle request RW 0x0 0x0: DLL in Power-down mode upon hardware idle request 0x1: DLL in DLL idle mode upon hardware idle request 0x2: No action upon hardware idle request. Input clock frequency must not be changed. 0x3: Reserved for future use (no action upon hardware idle request). 4 DLLIDLE Enables the DLL Idle mode RW 0x0 0x0: DLL Idle mode disabled 0x1: DLL Idle mode enabled 3 ENADLL Enables DLL RW 0x0 0x0: DLL disabled 0x1: DLL enabled 2 LOCKDLL Selects the DLL functionality between the TrackingDelay mode RW 0x0 (previously called lock mode) or the ModeFixedDelay mode (previously called unlock mode). The DLL mode is updated in the DLL cell after: - DLLIDLE mode - DLL power-down mode 0x0: LOCKDLL at 0 puts the DLL in TrackingDelay mode (tracking counter started). 0x1: LOCKDLL at 1 puts the DLL in ModeFixedDelay mode. The fixed delay defined in FIXEDDELAY bit field is used to delay DQS lines for read accesses. (1) The DLL characterization shows that this feature is not useful and that this value must be left at 0x0. 2302 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated RESERVED DLLMODEONIDLEREQ DLLIDLE ENADLL LOCKDLL RESERVED RESERVED
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Bits Field Name Description Type Reset 1 RESERVED Reserved RW 0x0 0 RESERVED Write 0s for future compatibility. Reads return zero. RW 0x0 Table 10-168. Register Call Summary for Register SDRC_DLLA_CTRL SDRAM Controller (SDRC) Subsystem • Power Management: [0] • Power-Saving Features: [1] [2] • DLL/CDL Configuration: [3] [4] [5] [6] [7] [8] • Memory Power Management: [9] [10] • SDRC Register Summary: [11] Address Offset 0x0000 0064 Table 10-169. SDRC_DLLA_STATUS Physical Address 0x6D00 0064 Instance SDRC Description This register reflects the current status of the DLL A. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Bits Field Name Description Type Reset 31:3 RESERVED Reads return zeros. R 0x00000000 2 LOCKSTATUS DLL lock status R 0x0 0x0: The DLL is not locked. 0x1: The DLL is locked. 1 RESERVED Reads return zero. R 0x0 0 RESERVED Reads return zero. R 0x0 Table 10-170. Register Call Summary for Register SDRC_DLLA_STATUS SDRAM Controller (SDRC) Subsystem • SDRC Register Summary: [0] Address Offset 0x0000 0070 Table 10-171. SDRC_POWER_REG Physical Address 0x6D00 0070 Instance SDRC Description This SDRC power-management register defines the global power-management policy (shared by CS0/CS1). Type RW SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated LOCKSTATUS RESERVED RESERVED 2303
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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