Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
MUX9<br />
System address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
Address mapping b1 b0<br />
13−bit<br />
row [12:0] 8−bit<br />
column [7:0]<br />
<strong>Memory</strong> address 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0<br />
MUX<strong>10</strong><br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
MUX11<br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
13−bit<br />
row [12:0] <strong>10</strong>−bit<br />
column [9:0]<br />
12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
12−bit<br />
row [11:0] <strong>10</strong>−bit<br />
column [9:0]<br />
11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
MUX12<br />
System address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
Address mapping b1 b0<br />
13−bit row [12:0]<br />
11−bit column [<strong>10</strong>:0]<br />
<strong>Memory</strong> address 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
MUX13<br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
MUX14<br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
MUX15<br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
MUX16<br />
System address<br />
Address mapping<br />
<strong>Memory</strong> address<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
b1 b0<br />
Public Version<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong> www.ti.com<br />
Figure <strong>10</strong>-45. SDRC SDR/DDR-SDRAM System Address Multiplexing Schemes (2 of 3)<br />
14−bit<br />
row [13:0]<br />
<strong>10</strong>−bit<br />
column [9:0]<br />
13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
13−bit<br />
row [12:0]<br />
<strong>10</strong>−bit<br />
column [9:0]<br />
12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
13−bit<br />
row [12:0]<br />
11−bit<br />
column [<strong>10</strong>:0]<br />
12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
14−bit<br />
row [13:0]<br />
<strong>10</strong>−bit<br />
column [9:0]<br />
13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
2214 <strong>Memory</strong> <strong>Subsystem</strong> SPRUGN4L–May 20<strong>10</strong>–Revised June 2011<br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
sdrc-005
Change language