Chapter 10 Memory Subsystem.pdf

Device
SDRAM controller
subsystem
Retiming
sdrc_nras
sdrc_ncas
sdrc_ncs[1:0]
sdrc_cke0
sdrc_nclk
sdrc_a[14:0]
sdrc_nwe
sdrc_ba[1:0]
sdrc_dm[3:0]
sdrc_dqs[3:0]
sdrc_d[15:0]
sdrc_d[31:16]
sdrc_cke1
sdrc_clk I/O
configuration
logic
System control
module
INPUTENABLE bit
Public Version
www.ti.com SDRAM Controller (SDRC) Subsystem
Figure 10-43. SDRC Subsystem Connections to DDR SDRAM
CAUTION
nRAS
nCAS
nCS(0)
CKE
CLK
nCLK
x16 DDR SDRAM
addr[14:0]
nWE
BA[1:0]
DM[1:0]
DQS[1:0]
DQ[15:0]
nRAS
nCAS
nCS(1)
CKE
CLK
nCLK
x32 DDR SDRAM
addr[14:0]
nWE
BA[1:0]
DQS[3:0]
DQ[15:0]
DQ[31:16]
DM[3:0]
Both memory types (SRD/DDR SDRAM) cannot be connected simultaneously
to the SDRC memory interface.
Table 10-95 lists SDRC subsystem I/O pins.
Table 10-95. SDRC Subsystem I/O Description
Pin Type Description
sdrc_d[31:0] I/O 32-bit wide data bus
sdrc_ba[1:0] O Bank address 1-0
sdrc_a[14:0] O Address bus
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
sdrc-003
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