Chapter 10 Memory Subsystem.pdf

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Device GPMC A[16:1]/D[15:0] nCS[2] nADV/ALE nOE/nRE nWE nBE0/CLE nBE1 nWP WAIT[2] CLK gpmc_d[15:0] gpmc_ncs[2] gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_nbe0_cle gpmc_nbe1 gpmc_nwp gpmc_wait[2] System control module INPUTENABLE bit I/O configuration logic Retiming clk Public Version General-Purpose Memory Controller www.ti.com NOTE: The device does not provide the A0 byte address line required for random-byte addressable 8-bit-wide device interfacing (for multiplexed and nonmultiplexed protocol). Hence, an 8-bit device must be connected to the D[7:0] / gpmc_d[7:0] data bus (rather than D[15:8] / gpmc_d[15:8]) of the GPMC. This limits the use of 8-bit-wide device interfacing to byte-alias access. Figure 10-3. GPMC to 16-Bit NAND Device gpmc_clk 16 D[15:0] nCS External device/ memory nADV/ALE nOE/nRE nWE CLE nWP R/nB CLK gpmc−003 NOTE: The device does not provide the A0 byte address line required for random-byte addressable 8-bit-wide device interfacing (for multiplexed and nonmultiplexed protocol). Hence, an 8-bit device must be connected to the D[7:0]/gpmc_d[7:0] data bus (rather than D[15:8]/gpmc_d[15:8]) of the GPMC. This limits the use of 8-bit-wide device interfacing to byte-alias accesses. Table 10-1 lists the GPMC subsystem I/O pins. Table 10-1. GPMC I/O Description Pin Name I/O Description gpmc_a[11:1] O Address gpmc_d[15:0] I/O Data gpmc_ncs[7:0] O Chip-selects (active low) gpmc_clk I/O Clock (1) gpmc_nadv_ale O Address valid (active low). Also used as address latch enable (active high) for NAND protocol memories. gpmc_noe_nre O Output enable (active low). Also used as read enable (active low) for NAND protocol memories. gpmc_nwe O Write enable (active low) gpmc_nbe0_cle O Lower-byte enable (active low). Also used as command latch enable for NAND protocol memories. (1) This output signal is also used as retiming input (the CONTROL_PADCONF_x.INPUTENABLE bit must be set to 1). 2098Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com General-Purpose Memory Controller Table 10-1. GPMC I/O Description (continued) Pin Name I/O Description gpmc_nbe1 O Byte 1 enable (active low) gpmc_nwp O Write protect (active low) gpmc_wait[3:0] I External wait signal for NOR and NAND protocol memories gpmc_io_dir O gpmc_d[15:0] signal direction control: Low during transmit (for write access: data OUT from GPMC to memory), High during receive (for read access: data IN from memory to GPMC) Table 10-2 shows the use of address and data GPMC pins based on the type of external device. Table 10-2. GPMC Pin Multiplexing Options GPMC Pin Multiplexed 16-Bit NAND 8-Bit NAND Address Data Device Device 16-Bit Device gpmc_a[11] A27 Not used Not used gpmc_a[10] A26 Not used Not used gpmc_a[9] A25 Not used Not used gpmc_a[8] A24 Not used Not used gpmc_a[7] A23 Not used Not used gpmc_a[6] A22 Not used Not used gpmc_a[5] A21 Not used Not used gpmc_a[4] A20 Not used Not used gpmc_a[3] A19 Not used Not used gpmc_a[2] A18 Not used Not used gpmc_a[1] A17 Not used Not used gpmc_d[15] A16/D15 D15 Not used gpmc_d[14] A15/D14 D14 Not used gpmc_d[13] A14/D13 D13 Not used gpmc_d[12] A13/D12 D12 Not used gpmc_d[11] A12/D11 D11 Not used gpmc_d[10] A11/D10 D10 Not used gpmc_d[9] A10/D9 D9 Not used gpmc_d[8] A9/D8 D8 Not used gpmc_d[7] A8/D7 D7 D7 gpmc_d[6] A7/D6 D6 D6 gpmc_d[5] A6/D5 D5 D5 gpmc_d[4} A5/D4 D4 D4 gpmc_d[3] A4/D3 D3 D3 gpmc_d[2] A3/D2 D2 D2 gpmc_d[1] A2/D1 D1 D1 gpmc_d[0] A1/D0 D0 D0 Enabling the GPMC.GPMC_CONFIG[1] LIMITEDADDRESS bit forces A[26:11] to 1 on the GPMC I/O side. Thus, only devices with 2 Kbytes of addressing space can be accessed using gpmc_a[11:1] . With all device types, the GPMC does not drive unnecessary address lines. They stay at their reset value of 0x00. Address mapping supports address/data-multiplexed 16-bit wide devices: • To minimize the number of IC pins required for the external memory connection, the NOR flash memory controller supports multiplexed address and data memory devices without adding logic externally. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2099
Page 1 and 2: This chapter describes the memory s
Page 3: Device GPMC External device/ memory
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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