Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
• SDRAM type
• Operating voltage
• Maximum operating frequency
• Maximum memory size
• Memory organization:
– Number of banks
– Data bus width
• Burst length
• Page size
• Column address strobe (CAS) latency
• Refresh rate
• AC timing parameters and especially the access time parameter tAC
These parameters are defined in the SDRAM device datasheet and must meet the SDRC specifications.
10.2.6.4.2 SDRC Characteristics
Keeping the SDRAM device settings in mind, the SDRC supports:
• Supported device type: Up to two mobile single data rate (M-SDR) SDRAMs, or up to two low-power
double data rate (LPDDR) SDRAMs.
• Maximum supported memory size: 128MB per external SDRAM bank (256- and 512-MB SDRAM may
be supported, depending on their implementation)
• Minimum supported memory size: 2MB
• Maximum SDRC addressing capability: 1GB
• Memory organization:
– Number of internal SDRAM banks: two (for 2-MB and 4-MB memory device only) or four banks
(other memory device only)
– Data path to external SDRAM memory: 16- or 32-bit
• Burst Length: Burst of 2 (M-SDR) and burst of 4 (LPDDR)
• Page size: Programmable value (up to 16K bytes)
• Column address strobe latency (CL): 1 to 5 system clock cycles
• Refresh intervals: Programmable value
• Major operation is 3-3-3 (CL-tRCD-tRP) conditions.
– CL = 3
– tRCD = 3 clocks cycle time
– tRP = 3 clocks cycle time
– tRRD = 2 clocks cycle time
– tRAS = 7 clocks cycle time
– tRC = 10 clocks cycle time
10.2.6.4.3 SDRAM Device Compatibility Verification
In this example, a mobile DDR SDRAM memory with the following characteristics is verified for
compatibilty:
• Type: Mobile DDR SDRAM
• Size: 512 Mbits (16M * 32 in 4 banks)
Table 10-110 lists the SDRAM versus the SDRC characteristics.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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