Chapter 10 Memory Subsystem.pdf

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M5 M6 M7 M8 Pooled spares Spares covered by ECC0 All ECC at the end (of page) Write Read Mode Size0 Size1 7 3 P E P E Pooled spares Spares covered by ECC0 All ECC at the end, left-padded Write Read Mode Size0 Size1 7 8 Pooled spares Spares not covered by ECC All ECC at the end Mode Size0 Size1 Write 6 0 Read 4 U E Pooled spares Spares not covered by ECC All ECC at the end, left-padded Mode Size0 Size1 Write 6 0 P 1+E P E U/S +E U/S +1+E Read 9 U E Public Version General-Purpose Memory Controller www.ti.com Figure 10-34. NAND Page Mapping and ECC: Pooled Spare Schemes Sector data Sector data Data0 Data1 Protected (pooled) Ecc0 Ecc1 512 bytes 512 bytes 0 1 0 1 Sector data Sector data 512 bytes 512 bytes P 1 E 1 E 512 bytes 512 bytes size1 size1 0 1 inactive 0 1 512 bytes 512 bytes 0 1 size1 inactive P E E size0 size1 size1 0 1 size0 size1 size1 size0 1 size1 1 size1 Data0 Data1 Unprotected (pooled) Ecc0 Ecc1 0 U E E size0 U size0 Pooled page spares Pooled page spares Pooled page spares Pooled page spares Data0 Data1 Unprotected (pooled) inactive inactive Data0 Data1 Protected (pooled) Pad Ecc0 Pad Ecc1 0 1 0 1 Sector data Sector data 0 1 Sector data Sector data 0 1 0 inactive size0 size1 size1 0 i. 0 i. 1 inactive 10.1.5.14.3.2.3.3 Per-Sector Spare Mapping, With ECC Separated at the End of the Page size1 size1 Pad Ecc0 Pad Ecc1 1 E 1 E size1 0 i. 1 1 size1 1 size1 In the schemes in Figure 10-35, each 512-byte sector of the main area is associated with two sections of the spare area. gpmc-034 • ECC section, all aligned at the end of the page • Other data section, aligned before the ECCs, each of which may or may not be protected by its sectors ECC 2160 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
M9 Per-sector spares, separate ECC Spares covered by sector ECC All ECC at the end Write Read Mode Size0 Size1 6 5 P E P E M Per-sector spares, separate ECC 10 Spares covered by sector ECC All ECC at the end, left-padded M 11 Write Read Mode Size0 Size1 6 11 P 1+E P E Per-sector spares, separate ECC Spares not covered by ECC All ECC at the end Mode Size0 Size1 Write 6 0 U+E Read 4 SU E M Per-sector spares, separate ECC 12 Spares not covered by ECC All ECC at the end, left-padded Mode Size0 Size1 Write 6 0 U+1+E Read 9 SU E Public Version www.ti.com General-Purpose Memory Controller Figure 10-35. NAND Page Mapping and ECC: Per-Sector Schemes, With Separate ECC 10.1.5.14.4 Prefetch and Write-Posting Engine Sector data Sector data Data0 Data1 Prot0 Prot1 Ecc0 Ecc1 512 bytes 512 bytes 0 1 512 bytes 512 bytes P P 1 E 1 E 512 bytes 512 bytes inactive size1 size1 0 1 inactive 0 1 512 bytes 512 bytes non-ECC spares P P E E 0 size0 size0 size1 size1 0 1 0 1 0 1 Sector data Sector data Data0 Data1 0 1 0 1 Sector data Sector data size0 size0 size1 U U E E size0 1 non-ECC spares Prot0 Prot1 0 size0 size0 0 1 size0 size0 non-ECC spares size1 ECC inactive inactive ECC Pad Ecc0 Pad Ecc1 U U 1 E 1 E size1 size1 inactive 0 i. size1 size1 size1 i. 0 i. 1 Data0 Data1 Unprot0 Unprot1 Ecc0 Ecc1 0 1 Sector data Sector data non-ECC spares Data0 Data1 0 1 size0 1 Unprot0 Unprot1 0 1 inactive ECC Pad Ecc0 Pad Ecc1 1 size1 1 size1 ECC size1 1 1 size1 1 size1 gpmc_035 NAND device data access cycles are usually much slower than the MCU system frequency; such NAND read or write accesses issued by the processor will impact the overall system performance, especially considering long read or write sequences required for NAND page loading or programming. To minimize this effect on system performance, the GPMC includes a prefetch and write-posting engine, which can be used to read from or write to any chip-select location in a buffered manner. The prefetch and write-posting engine uses an embedded 64 bytes (32 Word16) FIFO to prefetch data SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2161
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
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Page 65: M1 M2 M3 M4 Per-sector spares Spare
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Public Version www.ti.com SDRAM Con
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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