Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
Bits Field Name Description Type Reset
1 TERMINALCOUNTEVENT Enables TerminalCountEvent interrupt issuing in pre-fetch or RW 0x0
ENABLE write-posting mode
0x0: TerminalCountEvent interrupt is masked
0x1: TerminalCountEvent interrupt is not masked
0 FIFOEVENTENABLE Enables the FIFOEvent interrupt RW 0x0
0x0: FIFOEvent interrupt is masked
0x1: FIFOEvent interrupt is not masked
Table 10-38. Register Call Summary for Register GPMC_IRQENABLE
General-Purpose Memory Controller
• NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5]
• GPMC Register Summary: [6]
Address Offset 0x0000 0040
Table 10-39. GPMC_TIMEOUT_CONTROL
Physical Address 0x6E00 0040 Instance GPMC
Description The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUTSTARTVALUE
Bits Field Name Description Type Reset
31:13 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000
12:4 TIMEOUTSTARTVALUE Start value of the time-out counter RW 0x1FF
0x000: Zero GPMC_FCLK cycle
0x001: One GPMC_FCLK cycle
...
0x1FF: 511 GPMC_FCLK cycles
3:1 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0
0 TIMEOUTENABLE Enable bit of the TimeOut feature RW 0x0
0x0: TimeOut feature is disabled
0x1: TimeOut feature is enabled
Table 10-40. Register Call Summary for Register GPMC_TIMEOUT_CONTROL
General-Purpose Memory Controller
• Error Handling: [0] [1]
• GPMC Register Summary: [2]
• GPMC Register Description: [3]
2182 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated
RESERVED
TIMEOUTENABLE