Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
Wait-monitoring pipelining depth is similar to synchronous read access:
• At WRACCESSTIME completion if WAITMONITORINGTIME = 0
• The WAITMONITORINGTIME * (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before
WRACCESSTIME completion if WAITMONITORINGTIME =/ 0.
Wait-monitoring pipelining definition applies to whole burst accesses:
• WAIT monitored as active freezes the CYCLETIME counter. For accesses within a burst, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as active indicates that the data
bus is not being captured by the external device. Control signals are kept in their current state. The
data bus is kept in its current state.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. For accesses within a burst, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as inactive indicates the effective
data capture of the bus by the external device and starts the next access of the burst. In case of a
single access or if this was the last access in a multiple access cycle, all signals, including the data
bus, are controlled according to their related control timing value and the CYCLETIME counter status.
NOTE: Wait monitoring is supported for all configurations except for GPMC_CONFIG1_i[19:18]
WAITMONITORINGTIME = 0x 0 (where i = 0 to 7) for write bursts with a clock divider of 1 or
2 (GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER bit field equal to 0x0 or 0x1, respectively).
10.1.5.4.5 WAIT With NAND Device
For details about the use of the wait pin for communication with a NAND flash external device, see
Section 10.1.5.14.2, NAND Device-Ready Pin.
10.1.5.4.6 Idle Cycle Control Between Successive Accesses
10.1.5.4.6.1 Bus Turnaround (BUSTURNAROUND)
To prevent data-bus contention, an access that follows a read access to a slow memory/device (that is,
control the nCS/nOE de-assertion to data bus in high-impedance delay) must be delayed.
The bus turnaround is a time-out counter starting after nCS or nOE de-assertion time (whichever occurs
first) and delays the next access start-cycle time. It is programmed trhough the
GPMC.GPMC_CONFIG6_i[3:0] BUSTURNAROUND bit field (where i = 0 to 7).
After a read access to a chip-select with a non zero BUSTURNAROUND, the next access is delayed until
the BUSTURNAROUND delay completes, if the next access is one of the following:
• A write access to any chip-select (same or different from the chip-select data was read from)
• A read access to a different chip-select from the chip-select data was read access from
• A read or write access to a chip-select associated with an address/data-multiplexed device
Another way to prevent bus contention is to define an earlier nCS or nOE deassertion time for slow
devices or to extend the value of RDCYCLETIME. Doing this prevents bus contention, but affects all
accesses of this specific chip-select.
10.1.5.4.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN,
CYCLE2CYCLEDELAY)
Some devices require a minimum chip-select signal inactive time between accesses. The
GPMC.GPMC_CONFIG6_i[7] CYCLE2CYCLESAMECSEN bit (i = 0 to 7) enables insertion of a minimum
number of GPMC_FCLK cycles, defined by the GPMC.GPMC_CONFIG6_i[11:8] CYCLE2CYCLEDELAY
field, between successive accesses of any type (read or write) to the same chip-select.
If CYCLE2CYCLESAMECSEN is enabled, any subsequent access to the same chip-select is delayed until
its CYCLE2CYCLEDELAY completes. The CYCLE2CYCLEDELAY counter starts when
CSRDOFFTIME/CSWROFFTIME completes.
2120 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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