Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Public Version SDRAM Controller (SDRC) Subsystem www.ti.com When fixed delay mode is enabled, a counter (programmable through the SDRC_DLLA_CTRL [23:16]MODEFIXEDDELAYINITLAT field) based on the input frequency allows the SDRC to stall all incoming requests. Once this counter expires, the SDRC starts accessing the memory. The DLL characterization shows that this feature is not useful and that this value shall be set to 0x0, leading actually to a null delay. The DLL can be put in idle mode using the SDRC_DLLA_CTRL[4] DLLIDLE bit. When in idle mode, the DLL lock is lost. The precharge voltage is kept stable to enable faster relock when going back to a functional state. If set, this bit overrides the ENADLL bit. Thus, avoid completely powering down the DLL by keeping the precharge voltage and cutting off the analog loop. Exiting from this idle mode saves some clock cycles compared to exiting from power-down mode. Refer to the note (DLL behavior upon a warm reset assertion) in Section 10.2.4.4.9.2, Dynamic Low-Power Operating Modes). Furthermore, the SDRC_DLLA_CTRL[6:5] DLLMODEONIDLEREQ field defines the modes (power-down/DLLIDLE/No action) of the DLL that are automatically entered upon an Idle_req assertion. The DLL mode (TrackedDelay or ModeFixedDelay mode) is updated only when Idle_req/Idle_ack handshake protocol occurs, warm reset occurs, PWRDN is enabled, or DLLIDLE mode enabled. Power-down mode is asserted upon warm reset assertion. If power-down and DLLIDLE are asserted simultaneously, power-down overwrites DLLIDLE mode inside the DLLCDL cell. To modify the SDRC input clock when the DLL is locked and active, the DLL must first enter either its idle mode or its power-down mode. The SDRC input frequency can be changed by using any of the following scenarios: • Internal signals handshaking protocol with PRCM module • Warm reset event • DLLIDLE mode • Power-down mode The ENADLL bit controls the PWRDN mode of the DLL module. The LOCKDLL bit sets the DLL in TrackedDelay (lock) or ModeFixedDelay (unlock) mode. ModeFixedDelay mode is supported up to 83 MHz. See Section 10.2.4.4.11 for more information on the CDL/DLL module. DLLMODEONIDLEREQ is of no importance to the Idle_ack generation. In case DLLMODEONIDLEREQ = 2 and Idle_req occurs, Idle_ack can be generated and SDRC/core can go to idle; however, recovery from this state may be incorrectly performed and the DLL cannot relock. If this happens, the only solution to recover is to disable and then re-enable the DLL. DLLMODEONIDLEREQ = 2 is not a valid configuration under Idle_req assertion and must not be used. DLLMODEONIDLEREQ can be set 0 or 1, depending on whether the priority is shorter wake-up latency or lower power consumption. 10.2.5.3.5 Mode Register Programming and Modes of Operation The SDRC contains a group of registers known as the memory mode registers. These registers define the operational modes of the target SDRAM. • MR: Mode register used to define operational parameters common to SDR and DDR SDRAMs. • EMR1: Extended mode used to define operational parameters exclusive to DDR SDRAM (irrelevant to the SDRC since regular DDRs are not supported). • EMR2: Extended mode used to define operational parameters exclusive to mobile SDRAM. 10.2.5.3.5.1 Mode Register (MR) The 12-bit SDRC.SDRC_MR_p register (p = 0 or 1 for CS0 or CS1) is common to all SDR and DDR SDRAMs and controls the following parameters: • Write burst mode • CAS latency • Serial/interleaved mode • Burst length When programming the SDRC.SDRC_MR_p bit fields (where p = 0 or 1 for SDRC CS0 or CS1), consider the following: 2252 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem • CAS latencies of 1, 2, 3, 4, and 5 are supported (CASL). • Only serial mode (not interleaved mode) is supported (SIL = 0x0). • A burst length of 2 is supported for SDR SDRAM (BL = 0x2). • A burst length of 4 is supported for DDR SDRAM (BL = 0x4). • Burst lengths of 1 (BL = 0x0), 8 (BL =0x3), and full page (BL = 0x7) are not supported. Writing to SDRC.SDRC_MR_p initiates an implicit Load Mode register command qualified by BA1,BA0 = 0,0 except if the NOMEMORYMRS bit is set. 10.2.5.3.5.2 Extended Mode Register 2 (EMR2) The SDRC.SDRC_EMR2_p register (p = 0 or 1 for CS0 or CS1) is specific to mobile SDRAM devices. It is a 12-bit register that controls the following standard parameters: • Partial Array Self-Refresh (PASR) • Temperature Compensated Self-Refresh (TCSR) • Driver Strength (DS) The SDRC.SDRC_EMR2_p[2:0] PASR field programs the partial array self-refresh feature. The low power SDR SDRAM granularity is much finer than the granularity available in a mobile DDR SDRAM. The SDRC.SDRC_EMR2_p[4:3] TCSR field programs the temperature compensated self-refresh feature. The TCSR granularity available in a low power SDR is much finer than the granularity available in a mobile DDR. Writing to SDRC.SDRC_EMR2_p initiates an implicit load mode register command qualified by BA1, BA0 = 1,0 except if SDRC_SYSCONFIG[8] NOMEMORYMRS is set. 10.2.5.3.6 Autorefresh Management The SDRAM refresh configuration register group controls refresh management in normal operation. This group contains two SDRC.SDRC_RFR_CTRL_p registers that are defined on a per-CS basis and contain the following bit fields: • SDRC.SDRC_RFR_CTRL_p[1:0] ARE (where p = SDRC CS value 0 or 1) • SDRC.SDRC_RFR_CTRL_p[23:8] ARCV (where p = SDRC CS value 0 or 1) These bit fields can enable and disable autorefresh. Autorefresh bursts of 1, 4, and 8 are programmed using these fields. The autorefresh burst starts when the 16-bit autorefresh counter decrements to 0. The ARCV field loads the autorefresh counter with a 16-bit autorefresh value. The ARCV value is calculated using the following formula: Refresh value = (refresh interval / clock period / number of rows) - margin Note: Memory refresh interval in time unit. Margin is 50 (cycles). The margin considers the possibility of an ongoing access when the counter expires, thus delaying the effective refresh sequence. The value to be programmed is independent of the burst-refresh configuration: if a burst-refresh is configured, the value is automatically scaled in hardware to the burst-refresh size. Autorefresh is enabled by programming the SDRC.SDRC_MANUAL_p[3:0] CMDCODE field to 0x2 (where p = 0 or 1 for SDRC CS0 or CS1). 10.2.5.3.7 Page Closure Strategy The page closure strategy is defined on a per-bank basis by setting the SDRC.SDRC_POWER_REG[0] PAGEPOLICY bit. SDRC defines one type of page closure strategy: 1. High power/high bandwidth: Bandwidth consumption is critical. The SDRC tracks open pages. The SDRC determines whether the current access is an open page or a closed page. The SDRC does the following: SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2253
Page 1 and 2:
This chapter describes the memory s
Page 3 and 4:
Device GPMC External device/ memory
Page 5 and 6:
Public Version www.ti.com General-P
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
1 GBytes 512 MBytes 256 MBytes 128
Page 15 and 16:
Page 17 and 18:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 45 and 46:
Page 47 and 48:
nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50:
nCS nBE0/CLE nWE Public Version www
Page 51 and 52:
Page 53 and 54:
Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56:
512 Bytes input Row 0 Row 1 Row 2 R
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
M0 Manual mode Rd/Wr/ SW Mode Size0
Page 63 and 64:
Page 65 and 66:
M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68:
M9 Per-sector spares, separate ECC
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76:
Device GPMC module A [27:17] A [16:
Page 77 and 78:
FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80:
FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108: Public Version www.ti.com General-P
Page 109 and 110: Public Version www.ti.com General-P
Page 111 and 112: Public Version www.ti.com SDRAM Con
Page 115 and 116: Device SDRAM controller subsystem R
Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
Page 125 and 126: Configuration register file Rotatio
Page 131 and 132: Level 0 Region 0 Public Version www
Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152: CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 157: Public Version www.ti.com SDRAM Con
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170: Start configuration of VRFB context
Page 171 and 172: Initiator: Camera subsystem SDRC Su
Page 175 and 176: Request for transaction on class 1
Page 177 and 178: Class 1 and class 2 request for tra
Page 179 and 180: No A Class 0 empty? Yes Class 1 emp
Page 181 and 182: Status: There are n pending request
Page 183 and 184: 4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 209 and 210:
Public Version www.ti.com SDRAM Con
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222:
Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

Create successful ePaper yourself

Delete template?

Save as template?