Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0170 Table 10-139. SMS_ERR_ADDR Physical Address 0x6C00 0170 Instance SMS Description This register captures the address of an access that has generated an error. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRORADDRESS Bits Field Name Description Type Reset 31:0 ERRORADDRESS Access address that has generated an error (bit 31 is always 0) R 0x00000000 SDRAM Controller (SDRC) Subsystem • Error Logging: [0] • SMS Register Summary: [1] Address Offset 0x0000 0174 Table 10-140. Register Call Summary for Register SMS_ERR_ADDR Table 10-141. SMS_ERR_TYPE Physical Address 0x6C00 0174 Instance SMS Description This register provides additional information about the access that has generated the error. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED ERRORREGIONID RESERVED ERRORMCMD ERRORCONNID Bits Field Name Description Type Reset 31:27 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00 26:24 ERRORREGIONID ID of the region that has been illegally accessed R 0x0 0x0: Region 0 0x1: Region 1 ... 0x7: Region 7 0x8 to 0xF: reserved 23 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 22:20 ERRORMCMD Interconnect command that caused the error R 0x0 19:16 ERRORCONNID Identifies the illegal access initiator interconnect ConnID of the illegal R 0x0 access initiator. Refer to the top level documentation of the device using the SMS module 15:11 RESERVED Write 0s for future compatibility. RW 0x00 Read returns 0s. 2292 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 UNEXPECTEDADD Copyright © 2010–2011, Texas Instruments Incorporated UNEXPECTEDREQ ILLEGALCMD ERRORSECOVERLAP RESERVED RESERVED ERRORVALID
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Bits Field Name Description Type Reset 10 UNEXPECTEDADD Request targeting non-defined rotation contexts (such as contexts RW 0x0 12, 13, 14, or 15) or non-defined L3 Interconnect request signals used for context number decoding. Read 0x0: No unexpected request received Write 0x0: No effect Read 0x1: A request has been received on the interconnect with address decoding targeting rotation contexts 12, 13, 14, or 15, or a signal used for context number decoding was undefined. Write 0x1: Clear UNEXPECTEDADD bit. 9 UNEXPECTEDREQ Unexpected request received during SMS idle state RW 0x0 Read 0x0: No unexpected request received Write 0x0: No effect Read 0x1: A request has been received on the interconnect after the SMS was put in idle mode by the system power manager. Write 0x1: Clear the UNEXPECTEDREQ bit field. 8 ILLEGALCMD Illegal command on the L3 interface RW 0x0 Read 0x0: No illegal command received Write 0x0: No effect Read 0x1: Illegal command has been received. Write 0x1: Clear ILLEGALCMD bit field. 7:4 RESERVED Write 0s for future compatibility. RW 0x0 Read returns 0s. 3 ERRORSECOVERLAP Protection region overlapping error RW 0x0 Read 0x0: No overlap violation detected Write 0x0: No effect Read 0x1: A protection region overlap violation has been detected. Write 0x1: Clear ERRORSECOVERLAP bit field. 2 RESERVED Reserved for non-GP devices. RW 0x0 1 RESERVED Reserved for non-GP devices. RW 0x0 0 ERRORVALID Error validity status - Must be explicitly cleared with a write RW 0x0 transaction SDRAM Controller (SDRC) Subsystem • Violation Reporting: [0] • Error Logging: [1] [2] • SMS Register Summary: [3] Read 0x0: No effect Write 0x0: All error fields no longer valid Read 0x1: Error detected and logged in the other error fields Write 0x1: Clear ERRORVALID bit field Table 10-142. Register Call Summary for Register SMS_ERR_TYPE SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2293
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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