Chapter 10 Memory Subsystem.pdf

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SDRAM Controller (SDRC) Subsystem www.ti.com
The SDRC has three modes of automatic internal clock-gating behavior when the interconnect interface is
idle, that is. there are no outstanding active transactions in progress. These modes are controlled through
the SDRC.SDRC_POWER_REG[5:4] CLKCTRL and SDRC.SDRC_POWER_REG[23:8] AUTOCOUNT
fields.
• Mode 0: The autoclock gating feature is disabled. No internal clock gating is performed in the SDRC in
response to the detection of an idle state on the interconnect interface.
• Mode 1: A 16-bit counter starts decrementing when an interconnect idle condition is detected. The
counter start value is loaded from the AUTOCOUNT 16-bit field. When this counter times out, internal
clock gating within the SDRC is enabled.
• If an interconnect active command is received before the counter times out, or if an internal autorefresh
request is issued, the procedure is aborted, the counter stops decrementing, and the request is
serviced immediately.
• Mode 2: This mode is similar to mode 1, but before the internal clock gating, the SDRC places the
SDRAM into self-refresh mode and turns off the external SDRAM clock. This is the lowest power
mode.
To achieve maximum power savings, TI recommends the use of the PWDENA-, EXTCLKDIS-, and
CLKCTRL-related features.
Table 10-103 explains the different power-saving configurations that can be programmed with the
SDRC.SDRC_POWER_REG[3] EXTCLKDIS, SDRC.SDRC_POWER_REG[2] PWDENA, and
SDRC.SDRC_POWER_REG[5:4] CLKCTRL bits.
Table 10-103. Dynamic Power Saving Configurations
CLKCTRL EXTCLKDIS PWDENA CKE External SDRC CLK (1) SDRAM State Latency When
Exiting Power
Mode
0 0 0 Always high Always on Keep previous state
0 0 1 Low when no Always on Power-down Zero-latency penalty
access
0 1 0 Always high Off when no access Keep previous state
0 1 1 Low when no Off when no access Power-down One cycle penalty
access
1 0 0 Always high Always on Keep previous state
1 0 1 Low when no Always on Power-down Zero-latency penalty
access
1 1 0 Always high Off when no access Keep previous state
1 1 1 Low when no Off when no access Power-down One cycle penalty
access
2 0 0 Low when no Off when no access Enter self-refresh after
access after AUTOCOUNT AUTOCOUNT
expiration expiration
2 0 1 Low when no Off when no access Enter self-refresh after
access after AUTOCOUNT AUTOCOUNT
expiration expiration
2 1 0 Low when no Off when no access Enter self-refresh after
access AUTOCOUNT
expiration
2 1 1 Low when no Off when no access Enter self-refresh after
access AUTOCOUNT
expiration
(1) EXTCLK can be set to 1 all the time for power optimization purposes, except when manual commands are sent. In this case,
users must set EXTCLKDIS to 0 to ensure that a clock signal is provided to the memory device.
NOTE: When connected to a DDR memory, the SDRC never gates the clock provided to the DLL
components so that the DLL remains locked during these idle modes. This avoids the
maximum of 500 clock cycles latency required for relocking the DLL when the DLL clock is
switched off.
2240 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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