Chapter 10 Memory Subsystem.pdf

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www.ti.com SDRAM Controller (SDRC) Subsystem
10.2.3.1.1.2 SDRC
The SDRC is a single-clock domain module. The same clock is used for the interconnect and the memory
interface. The SDRC_CLK clock comes from the PRCM and runs at the L3 interconnect frequency.
SDRC_CLK is also used as a functional clock for the SDRC.
The SDRC_CLK clock source is the PRCM CORE_L3_ICLK output: CORE_L3_ICLK belongs to the L3
interconnect clock domain.
An SDRC_CLKX2 clock is provided by the PRCM at a double frequency of the SDRC_CLK clock. This
clock can be used in the LPDDR write path, depending on the configuration.
As a power-saving feature, when the SDRC no longer requires the clock domain, the software can disable
it at the PRCM level by setting the EN_SDRC bit in the PRCM.CM_ICKLEN1_CORE[1] register.
NOTE: The domain clock is shut down only if all other modules that receive the clock are capable
and ready to accept this idle request and have IdleAck asserted.
For details, see Chapter 3, Power, Reset, and Clock Management.
10.2.3.1.2 Hardware Reset
Global reset of the SDRC is done by activating the CORE_RST signal in the CORE_RST domain (see
Chapter 3, Power, Reset, and Clock Management).
There is one global reset signal, SDRC_GLOBALRESET, which is qualified by the signal
SDRC_POWERON. This qualification differentiates whether the signal is a cold reset or a warm reset.
• On a cold reset (that is, the power-on reset, when SDRC_POWERON = 0 and SDRC_GLOBALRESET
is applied), all registers and state-machines within the SDRC are asynchronously reset.
• On a warm reset (that is, any other system reset condition under control of the chip top-level power
manager, SDRC_POWERON = 1 when SDRC_GLOBALRESET is applied), the SDRC registers and
the FSM are not reset, but the external SDRAM memory can be optionally placed in self-refresh mode,
depending on the configuration of the SDRC.SDRC_POWER_REG[7] SRFRONRESET bit.
10.2.3.1.3 Software Reset
The SMS and SDRC modules can be reset under software control through the SMS.SMS_SYSCONFIG[1]
SOFTRESET and SDRC.SDRC_SYSCONFIG[1] SOFTRESET bits, respectively.
A software reset has the same action as a hardware cold reset; that is, the FSM and all registers are reset
immediately and unconditionally.
10.2.3.1.4 Power Management
The SDRC power is supplied by the CORE power domain. For details, see Chapter 3, Power, Reset, and
Clock Management.
The dynamic voltage and frequency scaling (DVFS) technic is described in the following section while
other power-saving features and different idle modes are described in Section 10.2.4.4, SDRC.
10.2.3.1.4.1 Dynamic Voltage and Frequency Scaling
If the input clock SDRC_CLK from the PRCM module is changed during operations, the DLL may enter an
undefined state and memory accesses may be corrupted. For this reason, it is necessary to manually
assert the SDRC_IDLEREQ signal before any clock frequency change. This manual access is done
through a register in the chip clock controller. The SDRC then finishes processing all open transactions. If
this option is activated in the SDRC_POWER_REG[6] SRFRONIDLEREQ bit, it puts the memory into
self-refresh. When done, it unlocks the DLL and puts it into a power-down state, through the
SDRC.SDRC_DLLA_CTRL[6:5] DLLMODEONIDLEREQ field. The SDRC then asserts the
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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