Chapter 10 Memory Subsystem.pdf

Public Version
www.ti.com SDRAM Controller (SDRC) Subsystem
– Fair arbitration between other system initiators (DMAs, video subsystem, GFX accelerator)
– Exclusive read-write transaction support
• SDRAM Controller
– Support for two independent CSs, with their corresponding register sets, and independent page
tracking
– Supports the following memory types:
• Mobile Single Data Rate SDRAM (M-SDR)
• Low-Power Double Data Rate SDRAM (LPDDR)
– Memory device capacity:
• 16 Mbits, 32 Mbits, 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits , 1 Gbit, 2 Gbits, and 4 Gbits
device support
– Memory device organization
• 2-bank support for 16 Mbits and 32 Mbits
• 4-bank support for 64 Mbits to 4 Gbits
• Flexible row/column address multiplexing schemes
• Bank linear addressing
• 16- or 32-bit data path to external SDRAM memory
• 1GB maximum addressing capability
• Device driver strength feature for mobile DDR supported
• New flexible address-muxing scheme lets users choose different bank mapping allocations by
configuring the bank and column address decoding ordering.
– Fully pipelined operation for optimal memory bandwidth usage
– Burst support
• Memory burst support
• System burst for SDR SDRAM: system burst translated into memory burst of 2
• System burst for mobile DDR SDRAM: system burst translated into memory burst size of 4
• Read interrupt by read, write interrupt by write
– CAS latency support 1, 2, 3, 4, 5
– Fully programmable ac timing parameters (on a per-parameter basis). Parameters are set
according to the memory interface clock frequency with respect to the attached memory device
timing specifications.
– Fine tuning of the controlled delay elements when operating with DDR memory
– Dynamic endianness support
– 9 * 64 bit lookahead FIFO in the SDRAM controller with a maximum of four transaction entries
– Low-power management support
• Dynamic power-saving features (internal clock gating)
• Static power-saving features
• Support for all standard low-power memory features
• Support for enhanced low-power features (mobile devices)
• Very low-power controlled-delay technology for optimal performance with DDR memory
• Can operate with mobile DDR memory at very low clock rates
– Autorefresh and self-refresh management
NOTE: The device does not support regular devices, SDR or DDR, because of electrical
incompatibility.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
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