Chapter 10 Memory Subsystem.pdf

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– The camera uses 8 * 64-bit burst size.
– The display uses 8 * 32-bit burst size.
– Double-indexing mode is selected.
• The physical address of the buffer in external memory is 0x8030 0000.
• The memory allocation for the buffer is 320 * 240- * 16-bit (or 160 * 240 * 32-bit).
• The camera subsystem uses its dedicated DMA channel 0.
• The display subsystem uses its video channel 1.
Configuring the VRFB Through the SMS Registers
The size of the page supported by the DDR32 memory is 1K byte, which is arranged as 32 * 32 bytes
page (width * height).
Configuring the page size:
• SMS_ROT_CONTROLn[6:4] PW = 5 (where n = 1)
• SMS_ROT_CONTROLn[10:8] PH = 5
Configuring the image parameters:
• SMS_ROT_SIZEn[10:0] IMAGEWIDTH = 160 (where n = 1)
• SMS_ROT_SIZEn[26:16] IMAGEHEIGHT = 256
• SMS_ROT_CONTROLn[1:0] PS = 2
Physical base address and rotation angle:
• SMS_ROT_PHYSICAL_BAn[30:0] PHYSICALBA = 0x8030 0000 (where n = 1).
The image data is accessed at the following virtual address range for 90-degree rotation: 0x7500 0000 -
0x75FF FFFF.
CAUTION
Image rotation using the YUV2 image format causes the stream to become
untidy. The display must be specifically configured to read and reorganize the
stream to conform to the YUV2 standard.
Tips for Configuring Successful Rotation
The following guidelines ensure optimal image rotation:
• Page arrangement:
Usually, the recommendation is to have a square page. If this is not possible, the longest page side
should correspond to the access direction that requires the maximum bandwidth; set the longest page
side to optimize the page break.
Using a 1024-byte page size, a 32 * 32-byte page arrangement is used as an example. With a 2K-byte
page organized as a 32 * 64 byte page, depending on the read or write operation, set the longest page
size to optimize the page break. If 0 is written and the 270-degree view is read, page height is greater
than page width (PH > PW). Set PH to 64 bytes (PH = 6).
• Virtual address memory arrangement:
When accessing image data through virtual addresses, the maximum line size supported by the VRFB
is 2,048 pixels.
In the memory buffer, the distance between two vertically adjacent pixels is fixed at 2,048 multiplied by
the pixel format in bytes. This means that when reading or writing image data through virtual
addresses, there must be an offset of: (2048 - IMAGEWIDTH) * PS bytes at the end of every line.
• Base address alignment:
For optimization, the base address is aligned on the page size. For instance, a 1K-byte page size
organized as a 32 * 32-byte page is aligned on 0x400 (to be adjusted on the base address).
• To improve performance on 90° rotation consider two things:
– Because a read access can appear more critical than a write access, a posted write may be
2266 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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