Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Transaction0 Duration of a transaction: How long to track the transaction? (it depends on the granularity settings) Arbitration decision on a transaction boundary: Which group has the priority? Public Version SDRAM Controller (SDRC) Subsystem www.ti.com 10.2.6.2.2 Arbitration Decision Figure 10-67. Arbitration Granularity Versus Arbitration Decision Transaction4 Transaction1 Transaction2 Transaction3 Transaction5 Transaction6 The SMS module controls arbitration. Requests from initiators for access to the external SDRAM are collected into several independent FIFO queues, and each queue is assigned to a class. Priority is then assigned to groups and classes; this defines the next request to be serviced. 10.2.6.2.2.1 Burst-Complete Mechanism The burst-complete mechanism applies granularity to the arbitration scheme. Access cannot be granted to a group within a class until a complete burst has been stored in the FIFO. Example: There is no ongoing transaction on Class 0. The initiator requests a 4 * 64-bit burst on Group 3 of Class 2 (SMS_CLASS_ARBITER2[27] BURST-COMPLETE = 0x1). Only 2 * 64-bit requests are stored in the FIFO. The mode of operation is: • Wait for the last 2 * 64-bit request to be stored in the FIFO. • Arbitration is requested once all requests of a burst have been received. • After the 4 * 64-bit burst is complete, the transaction occurs. • The arbitration choice mechanism resumes: – Were there any incoming requests during the last transaction? – What is the next request to be serviced/granted? 2268 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated Time t sdrc-024
Request for transaction on class 1 occurs during transaction of class 2 - group 3 Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Figure 10-68. BURST-COMPLETE On Class 2-Group 3 Group 0 Group 1 Group 2 Group 3 Group 7 ? ? ....... Lack of 2*64 bits requests 2*64 bits stored Request for transaction on class 0 occurs during transaction of class 2 - group 3. Group 6 Class 1 Class 2 Class 0 Class 2 - group 3 is granted for a burst of 4*64 bits. Wait for the last 2*64 bits requests to be stored before processing the complete burst transaction. Then check the incoming requests and wait for the arbitration decision to apply. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated sdrc-025 2269
Page 1 and 2:
This chapter describes the memory s
Page 3 and 4:
Device GPMC External device/ memory
Page 5 and 6:
Public Version www.ti.com General-P
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
1 GBytes 512 MBytes 256 MBytes 128
Page 15 and 16:
Page 17 and 18:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 45 and 46:
Page 47 and 48:
nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50:
nCS nBE0/CLE nWE Public Version www
Page 51 and 52:
Page 53 and 54:
Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56:
512 Bytes input Row 0 Row 1 Row 2 R
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
M0 Manual mode Rd/Wr/ SW Mode Size0
Page 63 and 64:
Page 65 and 66:
M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68:
M9 Per-sector spares, separate ECC
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76:
Device GPMC module A [27:17] A [16:
Page 77 and 78:
FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80:
FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Public Version www.ti.com SDRAM Con
Page 113 and 114:
Page 115 and 116:
Device SDRAM controller subsystem R
Page 117 and 118:
Page 119 and 120:
MUX1 System address 31 30 29 28 27
Page 121 and 122:
MUX23 System address Address mappin
Page 123 and 124: Public Version www.ti.com SDRAM Con
Page 125 and 126: Configuration register file Rotatio
Page 131 and 132: Level 0 Region 0 Public Version www
Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152: CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170: Start configuration of VRFB context
Page 171 and 172: Initiator: Camera subsystem SDRC Su
Page 173: Public Version www.ti.com SDRAM Con
Page 177 and 178: Class 1 and class 2 request for tra
Page 179 and 180: No A Class 0 empty? Yes Class 1 emp
Page 181 and 182: Status: There are n pending request
Page 183 and 184: 4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 219 and 220: Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222: Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

Create successful ePaper yourself

Delete template?

Save as template?