Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Address Offset 0x0000 0000 Table 10-113. SMS_REVISION Physical Address 0x6C00 0000 Instance SMS Description This register contains the IP revision code. IP revision code is defined at design time Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REV Bits Field Name Description Type Reset 31:8 RESERVED Read returns 0. R 0x000000 7:0 REV IP revision code R See (1) [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1 (1) TI internal data SDRAM Controller (SDRC) Subsystem • SMS Register Summary: [0] Address Offset 0x0000 0010 Table 10-114. Register Call Summary for Register SMS_REVISION Table 10-115. SMS_SYSCONFIG Physical Address 0x6C00 0010 Instance SMS Description This register controls the various parameters of the Interconnect. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Bits Field Name Description Type Reset 31:9 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000 8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 7:5 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0 4:3 SIDLEMODE Power management Req/Ack Control RW 0x0 0x0: Force Idle - An idle request is acknowledged unconditionally 0x1: No Idle - An idle request is never acknowledged. 0x2: Smart Idle - Acknowledgment to an idle request is based on the internal activity of the module 0x3: Reserved - Do not use. 2 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 1 SOFTRESET Software reset RW 0x0 0x0: Normal mode (no reset applied) 0x1: Software reset is activated 0 AUTOIDLE Internal interface clock gating strategy RW 0x1 0x0: Interface clock is free-running 0x1: Automatic interface clock gating strategy is applied, based on the interconnect activity 2284 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated RESERVED RESERVED SIDLEMODE RESERVED SOFTRESET AUTOIDLE
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-116. Register Call Summary for Register SMS_SYSCONFIG SDRAM Controller (SDRC) Subsystem • Software Reset: [0] • Module Power Saving: [1] [2] [3] • System Power Management: [4] [5] [6] [7] • SMS Register Summary: [8] Address Offset 0x0000 0014 Table 10-117. SMS_SYSSTATUS Physical Address 0x6C00 0014 Instance SMS Description This register provides module status, excluding interrupt status info. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED Bits Field Name Description Type Reset 31:8 RESERVED Reserved for module-specific status information. R 0x000000 Read returns 0s. 7:1 RESERVED Reserved for interconnect socket status information. R 0x00 Read returns 0s. 0 RESETDONE Internal reset monitoring R 0x- SDRAM Controller (SDRC) Subsystem • SMS Register Summary: [0] 0x0: Internal module reset is ongoing. 0x1: Reset complete. The module is ready to be used. Table 10-118. Register Call Summary for Register SMS_SYSSTATUS Table 10-119. SMS_RG_ATTi Address Offset 0x0000 0048 + (0x0000 0020 * i) Index i = 0 to 7 Physical Address 0x6C00 0048 + (0x0000 0020 * i) Instance SMS Description Request information permission Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REQINFO Bits Field Name Description Type Reset 31:0 REQINFO Request information permission RW 0x-------- The REQINFO field is a bit vector of permissions, one per MReqInfo encoding: NonHost/Host - User/Supervisor - Functional/Debug - Data Transfer/Opcode Fetch (1) (1) See Table 10-99 for more information on REQINFO values SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated RESETDONE 2285
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
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Page 143 and 144: Endianism CSnMUXCFG field SDRC.SDRC
Page 149 and 150: CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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