Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
from the NAND device in read mode (prefetch mode) or to store host data to be programmed into the
NAND device in write mode (write-posting mode). The FIFO draining and filling (read and write) can be
controlled either by the MCU through interrupt synchronization (an interrupt is triggered whenever a
programmable threshold is reached) or the sDMA through DMA request synchronization, with a
programmable request byte size in both prefetch or posting mode.
The prefetch and write-posting engine includes a single memory pool. Therefore, only one mode, read or
write, can be used at any given time. In other words, the prefetch and write-posting engine is a
single-context engine that can be allocated to only one chip-select at a time for a read prefetch or a
write-posting process.
The engine does not support atomic command and address phase programming and is limited to linear
memory read or write access. In consequence, it is limited to NAND data-stream access. The engine
relies on the MCU NAND software driver to control block and page opening with the correct data address
pointer initialization, before the engine can read from or write to the NAND memory device.
Once started, the engine data reads and writes sequencing is solely based on FIFO location availability
and until the total programmed number of bytes is read or written.
Any host-concurrent accesses to a different chip-select are correctly interleaved with ongoing engine
accesses. The engine has the lowest priority access so that host accesses to a different chip-select do not
suffer a large latency.
A round-robin arbitration scheme can be enabled to ensure minimum bandwidth to the prefetch and
write-posting engine in the case of back-to-back direct memory requests to a different chip-select. If the
GPMC.GPMC_PREFETCH_CONFIG1[23] PFPWENROUNDROBIN bit is enabled, the arbitration grants
the prefetch and write posting engine access to the GPMC bus for a number of requests programmed in
the GPMC.GPMC_PREFETCH_CONFIG1[19:16] PFPWWEIGHTEDPRIO field.
The prefetch and write-posting engine is dedicated to data-stream access (as opposed to random data
access). The engine does not include an address generator, and the request is limited to chip-select target
identification. The prefetch/write-posting engine read or write request is routed to the access engine with
the chip-select destination ID. After the required arbitration phase, the access engine processes the
request as a single access with the data access size equal to the device size specified in the
corresponding chip-select configuration.
NOTE: The destination chip-select configuration must be set to the NAND protocol-compatible
configuration for which address lines are not used (the address bus is not changed from its
current value). Selecting a different chip-select configuration can produce undefined
behavior.
10.1.5.14.4.1 General Basic Programming Model
The engine can be configured only if the GPMC.GPMC_PREFETCH_CONTROL[0] STARTENGINE bit is
de-asserted.
The engine must be correctly configured in prefetch or write-posting mode and must be linked to a NAND
chip-select before it can be started. The chip-select is linked using the
GPMC.GPMC_PREFETCH_CONFIG1[26:24] ENGINECSSELECTOR field.
In both prefetch and write-posting modes, the engine uses byte or Word16 access requests, respectively,
for an 8- or 16-bit-wide NAND device attached to the linked chip-select. The FIFOTHRESHOLD and
TRANSFERCOUNT fields must be programmed accordingly as a number of bytes.
When the GPMC.GPMC_PREFETCH_CONFIG1[7] ENABLEENGINE bit is set, the FIFO entry on the L3
interconnect port side is accessible at any address in the associated chip-select memory region. When the
ENABLEENGINE bit is set, any host access to this chip-select is rerouted to the FIFO input. Directly
accessing the NAND device linked to this chip-select from the host is still possible through the
GPMC.GPMC_NAND_COMMAND_i, GPMC.GPMC_NAND_ADDRESS_i, and
GPMC.GPMC_NAND_DATA_i registers (where i = 0 to 7).
The FIFO entry on the L3 interconnect port can be accessed with byte, Word16, or Word32 access size,
according to little-endian format, even though the FIFO input is 32-bit wide.
2162 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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