Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Table 10-151. SDRC Instance Summary Module Name Base Address Size SDRC 0x6D00 0000 64K bytes 10.2.8.2 SDRC Register Summary Table 10-152 summarizes the SDRC register mapping. Table 10-152. SDRC Register Summary Register Name Type Register Width (Bits) Address Offset Physical Address SDRC_REVISION R 32 0x0000 0000 0x6D00 0000 SDRC_SYSCONFIG RW 32 0x0000 0010 0x6D00 0010 SDRC_SYSSTATUS R 32 0x0000 0014 0x6D00 0014 SDRC_CS_CFG RW 32 0x0000 0040 0x6D00 0040 SDRC_SHARING RW 32 0x0000 0044 0x6D00 0044 SDRC_ERR_ADDR R 32 0x0000 0048 0x6D00 0048 SDRC_ERR_TYPE RW 32 0x0000 004C 0x6D00 004C SDRC_DLLA_CTRL RW 32 0x0000 0060 0x6D00 0060 SDRC_DLLA_STATUS R 32 0x0000 0064 0x6D00 0064 SDRC_POWER_REG RW 32 0x0000 0070 0x6D00 0070 SDRC_MCFG_p (1) RW 32 0x0000 0080 0x6D00 0080 + (0x0000 0030 * p) + (0x0000 0030 * p) SDRC_MR_p (1) RW 32 0x0000 0084 0x6D00 0084 + (0x0000 0030 * p) + (0x0000 0030 * p) SDRC_EMR2_p (1) RW 32 0x0000 008C 0x6D00 008C + (0x0000 0030 * p) + (0x0000 0030 * p) SDRC_ACTIM_CTRLA_p (1) RW 32 0x0000 009C 0x6D00 009C + (0x0000 0028 * p) + (0x0000 0028 * p) SDRC_ACTIM_CTRLB_p (1) RW 32 0x0000 00A0 0x6D00 00A0 + (0x0000 0028 * p) + (0x0000 0028 * p) SDRC_RFR_CTRL_p (1) RW 32 0x0000 00A4 0x6D00 00A4 + (0x0000 0030 * p) + (0x0000 0030 * p) SDRC_MANUAL_p (1) RW 32 0x0000 00A8 0x6D00 00A8 + (0x0000 0030 * p) + (0x0000 0030 * p) (1) p = 0 to 1. 10.2.8.3 SDRC Register Description This section provides a description of SDRC registers. Address Offset 0x0000 0000 Table 10-153. SDRC_REVISION Physical Address 0x6D00 0000 Instance SDRC Description This register contains the IP revision code. This code is specified at design time. Type R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED REV 2296 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Bits Field Name Description Type Reset 31:8 RESERVED Read returns 0. R 0x000000 7:0 REV IP revision code R See (1) [7:4]: Major revision [3:0]: Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1 (1) TI internal data SDRAM Controller (SDRC) Subsystem • IP Revision: [0] • SDRC Register Summary: [1] Address Offset 0x0000 0010 Table 10-154. Register Call Summary for Register SDRC_REVISION Table 10-155. SDRC_SYSCONFIG Physical Address 0x6D00 0010 Instance SDRC Description This register controls the various parameters of the interconnect. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Bits Field Name Description Type Reset 31:9 RESERVED Write 0s for future compatibility RW 0x000000 Read returns 0. 8 NOMEMORYMRS No external memory MRS command RW 0x0 0x0: When set to 0, the SDRC internal SDRC_MR_p and SDRC_EMR2_p registers (both CS) are written and MR, EMR2 commands are performed to the corresponding registers of the external SDRAM. 0x1: When set to 1, only SDRC internal SDRC_MR_p and SDRC_EMR2_p registers (both CS) are written, no MR or EMR2 commands are performed to SDRAM. 7:5 RESERVED Write 0s for future compatibility. RW 0x0 Read returns 0. 4:3 IDLEMODE Power management Req/Ack control RW 0x2 0x0: Reserved - Do not use. 0x1: Reserved - Do not use. 0x2: Smart Idle - Acknowledgment to an idle request is based on the internal activity of the module. Issued when the SDRC enters self-refresh. 0x3: Reserved - Do not use. 2 RESERVED Write 0s for future compatibility. Read returns 0 RW 0x0 1 SOFTRESET Software reset RW 0x0 0x0: Normal mode (no reset applied) 0x1: Software reset activated 0 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated NOMEMORYMRS RESERVED IDLEMODE RESERVED SOFTRESET RESERVED 2297
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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