Chapter 10 Memory Subsystem.pdf

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10.1.4.5 Prefetch and Write-Posting Engine
The prefetch and write-posting engine is a simplified embedded-access requester that presents requests
to the access engine on a user-defined chip-select target. The access engine interleaves these requests
with any request coming from the L3 interface; as a default the prefetch and write-posting engine has the
lowest priority.
The prefetch and write-posting engine is dedicated to data-stream access (as opposed to random data
access); thus, it is primarily dedicated to NAND support. The engine does not include an address
generator; the request is limited to chip-select target identification. It includes a 64-byte FIFO associated
with a DMA request synchronization line, for optimal DMA-based use.
For more information about prefetch and write-posting engine programming, see Section 10.1.5.14.4,
Prefetch and Write-Posting Engine.
10.1.4.6 External Device/Memory Port Interface
The external port interface controls all address, data, and control signals required for communication with
GPMC-supported devices and memories.
10.1.5 GPMC Basic Programming Model
The GPMC basic programming model offers maximum flexibility to support various access protocols for
each of the eight configurable chip-selects. Use optimal chip-select settings, based on the characteristics
of the external device:
• Different protocols can be selected to support generic asynchronous or synchronous random-access
devices (NOR flash, SRAM) or to support specific NAND devices.
• The address and the data bus can be multiplexed on the same external bus.
• Read and write access can be independently defined as asynchronous or synchronous.
• System requests (byte, Word16, burst) are performed through single or multiple accesses. External
access profiles (single, multiple with optimized burst length, native- or emulated-wrap) are based on
external device characteristics (supported protocol, bus width, data buffer size, native-wrap support).
• System burst read or write requests are synchronous-burst (multiple-read or multiple-write). When
neither burst nor page mode is supported by external memory or ASIC devices, system burst read or
write requests are translated to successive single synchronous or asynchronous accesses (single
reads or single writes). 8-bit-wide devices are supported only in single-synchronous or asynchronous
read or write mode.
• To simulate a programmable internal-wait state, an external wait pin can be monitored to dynamically
control external access at the beginning (initial access time) of and during a burst access.
Each control signal is controlled independently for each chip-select. The internal functional clock of the
GPMC (GPMC_FCLK) is used as a time reference to specify the following:
• Read- and write-access duration
• Most GPMC external interface control-signal assertion and deassertion times
• Data-capture time during read access
• External wait-pin monitoring time
• Duration of idle time between accesses, when required
10.1.5.1 Chip-Select Base Address and Region Size Configuration
Any external memory or ASIC device attached to the GPMC external interface can be accessed by any
device system host within the GPMC 1-GB contiguous address space. For details, see Chapter 2 Memory
Mapping.
The GPMC 1-GB address space can be divided into a maximum of eight chip-select regions with
programmable base address and programmable CS size. The CS size is programmable from 16MB to
256MB (must be a power-of-2) and is defined by the mask field. Attached memory smaller than the
programmed CS region size is accessed through the entire CS region (aliasing).
2106 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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