Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
Table 10-26 summarizes the level of the NOR interface signals applied to external devices or memories.
Table 10-26. NOR Interface Bus Operations Summary
Bus operation CLK nADV nCS nOE nWE WAIT DQ[15:0]
Read (asynchronous) x L L L H Asserted Output
Read (synchronous) Running L L L H Driven Output
Read (burst suspend) Halted x L H H Active Output
Write x L L H L Asserted Input
Output disable x x L H H Asserted High-Z
Standby x x H x x High-Z High-Z
10.1.6.2.1.4 Other Technologies
Other supported device types interact with the GPMC through the NOR interface protocol.
OneNAND is a high density and low-power memory device. OneNAND is based on a single- or
multilevel-cell NAND core with SRAM and logic, and interfaces as a synchronous NOR flash; it also has
synchronous write capability. It reads faster than conventional NAND and writes faster than conventionnal
NOR flash. Therefore, it is appropriate for both mass storage and code storage.
pSRAM is a low-power memory device for mobile applications. pSRAM is based on the DRAM cell with
internal refresh and address control features, and interfaces as a synchronous NOR flash; it also has
synchronous write capability.
10.1.6.2.1.5 Supported Protocols
The GPMC supports the following interface protocols when communicating with external memory or
external devices:
• Asynchronous read/write access
• Asynchronous read page access (4-8-16 Word16)
• Synchronous read/write access
• Synchronous read burst access without wrap capability (4-8-16 Word16)
• Synchronous read burst access with wrap capability (4-8-16 Word16)
10.1.6.2.2 GPMC Features and Settings
This section lists the GPMC features and settings:
• Supported device type: up to eight NAND or NOR protocol external memories or devices
• Operating voltage: 1.8 V
• Maximum operating frequency provided externally: up to 100 MHz (single device) with an L3-clock of
100 MHz. Up to 83 MHz (L3-clock divided by two) with an L3-clock of 166 MHz.
• Maximum GPMC addressing capability: 1 GB divided into eight chip-selects
• Maximum supported memory size: 256 MB (must be a power-of-2)
• Minimum supported memory size: 16 MB (must be a power-of-2). Aliasing occurs when addressing
smaller memories.
• Data path to external memory or device: 8- and 16-bit wide
• Burst and page access: burst of 4-8-16 Word16
• Supports bus keeping and bus turnaround
10.1.7 GPMC Register Manual
10.1.7.1 GPMC Instance Summary
Table 10-27 describes the GPMC instance.
2176 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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