Chapter 10 Memory Subsystem.pdf

OCP slave
interface
OCP slave
port
Command
interface
Refresh
module
DLL
module
CREQ
CACK
RREQ
RACK
Public Version
www.ti.com SDRAM Controller (SDRC) Subsystem
10.2.4.4.1 CS0-CS1 Memory Spaces
10.2.4.4.1.1 Chip-Select 0 Start Address
Figure 10-50. SDRC Architecture
Configuration
Power
management
Bank tracking
Controller
state-machine
Status
ac timing
parameters
SDRAM
control
signal
interface
RW
data path
SDRAM
Control signals
DATAOUT
DATAIN
• CS0 always starts at address 0 with respect to the local interconnect address.
• The valid CS0 range is 0 - CS0max, where CS0max is defined in the SDRC.SDRC_MCFG_p[17:8]
RAMSIZE field where p = 0 (for CS0), and by the number of banks.
10.2.4.4.1.2 Chip-Select 1 Start Address
• CS1 start address is programmable.
• The default base address for CS1 after reset is defined in the register description.
• The SDRC 1G-byte/8G-bit address space is segmented so that 7 possible CS1 start address locations
(8 in total minus 1 reserved for CS0) are defined by the SDRC.SDRC_CS_CFG[3:0] CS1STARTHIGH
field as shown in Figure 10-51.
• Each 128M-byte address space is also segmented into 32M-byte address spaces defined by the
SDRC.SDRC_CS_CFG[9:8] CS1STARTLOW field so that 64 possible CS1 start address locations are
defined by the SDRC.SDRC_CS_CFG[3:0] CS1STARTHIGH and SDRC.SDRC_CS_CFG[9:8]
CS1STARTLOW fields.
• The valid CS1 range is:
CS1 start address slot - CS1max, where CS1max is defined by SDRC.SDRC_MCFG_p[17:8]
RAMSIZE where p = 1 (for CS1) and SDRC.SDRC_CS_CFG registers.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
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