Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
NAND device-command and address-phase programming is achieved through write requests to the
GPMC.GPMC_NAND_COMMAND_i and GPMC.GPMC_NAND_ADDRESS_i register locations (i = 0 to 7)
with the correct command and address values. These locations are mapped in the associated chip-select
register region. The associated chip-select signal timing control must be programmed according to the
NAND device timing specification.
Command and address values are not latched during the access and cannot be read back at the register
location.
• Only write accesses must be issued to these locations, but the GPMC does not discard any read
access. Accessing a NAND device with nOE and CLE or ALE asserted (read access) can produce
undefined results.
• Write accesses to the GPMC.GPMC_NAND_COMMAND_i register location and to the
GPMC.GPMC_NAND_ADDRESS_i register location must be posted for faster operations (i = 0 to 7).
The GPMC.GPMC_CONFIG[0] NANDFORCEPOSTEDWRITE bit enables write accesses to these
locations as posted, even if they are defined as nonposted.
A write buffer is used to store write transaction information before the external device is accessed:
• Up to eight consecutive posted write accesses can be accepted and stored in the write buffer.
• For nonposted write, the pipeline is one deep.
• An GPMC.GPMC_STATUS[0] EMPTYWRITEBUFFERSTATUS bit stores the empty status of the write
buffer.
GPMC.GPMC_NAND_COMMAND_i and GPMC.GPMC_NAND_ADDRESS_i (i = 0 to 7) are Word32
locations, which means any Word32 or Word16 access is split into 4- or 2-byte accesses if an 8-bit wide
NAND device is attached. For multiple-command phase or multiple-address phase, the software driver can
use Word32 or Word16 access to these registers, but it must account for the splitting and little-endian
ordering scheme. When only one byte command or address phase is required, only byte write access to
GPMC.GPMC_NAND_COMMAND_i and GPMC.GPMC_NAND_ADDRESS_i can be used, and any of the
four byte locations of the registers are valid.
The same applies to a GPMC.GPMC_NAND_COMMAND_i and a GPMC.GPMC_NAND_ADDRESS_i (i =
0 to 7) Word32 write access to a 16-bit wide NAND device (split into two Word16 accesses). In the case
of a Word16 write access, the MSByte of the Word16 value must be set according to the NAND device
requirement (usually 0). Either Word16 location or any one of the four byte locations of the registers is
valid.
10.1.5.14.1.3 Command Latch Cycle
Writing data at the GPMC.GPMC_NAND_COMMAND_i location (i = 0 to 7) places the data as the NAND
command value on the bus, using a regular asynchronous write access.
• nCE is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• CLE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
• nWE is controlled by the WEONTIME and WEOFFTIME timing parameters.
• ALE and nRE (nOE) are maintained inactive.
Figure 10-22 shows the NAND command latch cycle.
2140 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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