Chapter 10 Memory Subsystem.pdf

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SDRAM Controller (SDRC) Subsystem www.ti.com
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AUTOCOUNT
WAKEUPPROC
RESERVED
Bits Field Name Description Type Reset
31:27 RESERVED Write 0s for future compatibility. RW 0x00
Read returns 0.
26 WAKEUPPROC Select if after a SDRC wakeup in DDR mode (in DLL tracking-delay RW 0x0
mode), the first request is stalled during 500 cycles latency or until the
lock signal from the DLL/CDL analog cell is asserted.
0x0: SDRC allows DDR access after 500 L3 clock cycles.
0x1: SDRC allows DDR access as soon as DLL LOCKSTATUS bit is 1.
25:24 RESERVED Write 0s for future compatibility. RW 0x0
Read returns 0.
23:8 AUTOCOUNT 16-bit programmable count value used for delayed automatic clock RW 0x0000
gating and self-refresh entry, assuming CLKCTRL field is not 0
7 SRFRONRESET Enter self refresh when a warm reset is applied: RW 0x1
0x0: Feature disabled
0x1: Feature enabled
6 SRFRONIDLEREQ Enter self refresh when on hardware idle request: RW 0x0
0x0: Feature disabled
0x1: Feature enabled
5:4 CLKCTRL Clock control feature defines clock gating and self refresh: RW 0x0
0x0: No auto clk feature turned on
0x1: Enable internal clock gating on timeout of Auto_cnt
0x2: Enable self-refresh on timeout of Auto_cnt
0x3: Reserved
3 EXTCLKDIS Disable the clock provided to the external memories: RW 0x0
0x0: Enable clock
0x1: Disable clock- Logical 0 is applied.
2 PWDENA Activate the power-down mode of the target memory through CKE pin. RW 0x1
0x0: Power-down mode feature disabled
0x1: Power-down mode feature enabled
1 RESERVED Write 0 for future compatibility. Read returns 0. RW 0x0
0 PAGEPOLICY Page/segment closure policy with respect to power versus bandwidth RW 0x1
trade-off - Must be set to 1
0x0: Reserved - must not be used
0x1: High-power/high bandwidth mode (HPHB)
Table 10-172. Register Call Summary for Register SDRC_POWER_REG
SDRAM Controller (SDRC) Subsystem
• Hardware Reset: [0]
• Power Management: [1]
• Refresh Management: [2]
• Power-Saving Features: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
• Reset Behavior: [15] [16]
• Page Closure Strategy: [17]
• Memory Power Management: [18] [19] [20]
• SDRC Register Summary: [21]
2304Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
Copyright © 2010–2011, Texas Instruments Incorporated
SRFRONRESET
SRFRONIDLEREQ
CLKCTRL
EXTCLKDIS
PWDENA
RESERVED
PAGEPOLICY