Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Table 10-95. SDRC Subsystem I/O Description (continued) Pin Type Description sdrc_ncs[1:0] O Chip-select 1-0 (active low) sdrc_clk O Clock (1) sdrc_nclk O Clock invert (DDR only) sdrc_cke0 O Clock enable (CS0) sdrc_cke1 O Clock enable (CS1) sdrc_nras O Row address strobe (active low) sdrc_ncas O Column address strobe (active low) sdrc_nwe O Write enable (active low) sdrc_dm[3:0] O Data mask/OE for SDR read operation sdrc_dqs[3:0] I/O Data output strobe (DDR only) (1) This output signal is also used as retiming input (the CONTROL_PADCONF_x.INPUTENABLE bit must be set to 1). 10.2.2.2 External Interface Configuration 10.2.2.2.1 CS0, CS1 Memory Spaces The SDRC can be connected independently to two external SDRAM memories. Mobile SDR SDRAM memory is supported in sizes of 16 Mbits, 32 Mbits, 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, 2 Gbits, and 4 Gbits. See Section 10.2.4.4.1 for more information on CS memory spaces. NOTE: The device does not support regular devices, SDR or DDR (see Section 10.2.5.3.1, Chip-Select Configuration). 10.2.2.2.2 AC Timing Control The SDRC permits the configuration of many of the ac timing parameters controlling the SDRAM transaction timing. It is required to adapt the transaction timing parameters to any memory device attached to the SDRC. A totally independent, complete set of parameters exists for each CS. The ac parameters and their quantification are summarized in Section 10.2.5.3.1, Chip-Select Configuration. 10.2.2.2.3 Address Multiplexing A flexible address scheme has been added to support any new type of address scheme and SDRAM density. This new address-muxing scheme lets users choose a different bank mapping allocation by configuring the order of the bank and row address decoding (column address always remains the same). The SDRC.SDRC_MCFG_p[7:6] BANKALLOCATION field defines the order of the bank and row decoding of the incoming system address. The BANKALLOCATION field can be set on a CS basis. For more details about the flexible address scheme, see Section 10.2.4.4.3, Address Multiplexing. The programming model is compatible with the legacy fixed address scheme and with the new flexible address scheme. This section describes the fixed address multiplexing configurations for both SDRAM components. The legacy fixed address scheme is selected when the SDRC.SDRC_MCFG_p[19] ADDRMUXLEGACY bit is set to 0 (where p = 0 or 1 for SDRC CS0 or CS1). The fixed address multiplexing configurations are described in this section, for both SDRAM components. An address multiplexing scheme is chosen by programming the SDRC.SDRC_MCFG_p[24:20] ADDRMUX field of the SDRC_MEMCFG registers on a per chip select basis (p = 0 or 1 for CS0 or CS1). Table 10-96 and Table 10-97 show all predefined address multiplexing schemes for SDRAM memory components. 2210 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-96. SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations (x16 Memory Interface) x16 Memory Interface Banks Column Row MUX Total Size Number of Device Address Address Scheme (MBits) Devices Organization BA0 1 A0-A7 8 A0-A10 11 MUX1 16 1 1M x 16 BA0 1 A0-A7 8 A0-A11 12 MUX2 32 1 2M x 16 BA1, 2 A0-A7 8 A0-A11 12 MUX2 64 1 4M x 16 BA0 BA1, 2 A0-A8 9 A0-A11 12 MUX4 128 2 8M x 8 BA0 1 8M x 16 BA1, 2 A0-A8 9 A0-A12 13 MUX7 256 1 16M x 16 BA0 BA1, 2 A0-A8 9 A0-A13 14 MUX26 512 1 32M x 16 BA0 BA1, 2 A0-A9 10 A0-A11 12 MUX6 256 2 16M x 8 BA0 1 16M x 16 BA1, 2 A0-A9 10 A0-A12 13 MUX10 512 2 32M x 8 BA0 10 1 32M x 16 BA1, 2 A0-A9 10 A0-A13 14 MUX13 1024 1 64M x 16 BA0 BA1, 2 A0-A9; A11 11 A0-A12 13 MUX12 1024 2 64M x 8 BA0 1 64M x 16 Table 10-97. SDRC Address Multiplexing Scheme Selection vs SDRAM Configurations (x32 Memory Interface) x32 Memory Interface Banks Column Row MUX Total Size Number of Device Address Address Scheme (MBits) Devices Organization BA0 1 A0-A7 8 A0-A11 12 MUX5 64 2 2M x 16 1 2M x 32 BA1, 2 A0-A7 8 A0-A10 11 MUX3 64 1 2M x 32 BA0 BA1, 2 A0-A7 8 A0-A11 12 MUX5 128 1 4M x 32 BA0 BA1, 2 A0-A7 8 A0-A12 13 MUX9 256 1 8M x 32 BA0 BA1, 2 A0-A7 8 A0-A13 14 MUX27 512 1 16M x 32 BA0 BA1, 2 A0-A7 8 A0-A14 15 MUX28 1024 1 32M x 32 BA0 BA1, 2 A0-A8 9 A0-A11 12 MUX8 256 4 8M x 8 BA0 2 8M x 16 1 8M x 32 BA1, 2 A0-A8 9 A0-A12 13 MUX24 512 1 16M x 32 BA0 BA1, 2 A0-A8 9 A0-A13 14 MUX23 1024 1 32M x 32 BA0 BA1, 2 A0-A8 9 A0-A14 15 MUX25 2048 1 64M x 32 BA0 SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem2211 Copyright © 2010–2011, Texas Instruments Incorporated
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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M0 Manual mode Rd/Wr/ SW Mode Size0
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