Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com 10.1.5.4.2 Wait Monitoring During an Asynchronous Write Access When wait-pin monitoring is enabled for write accesses (GPMC.GPMC_CONFIG1_i[21] WAITWRITEMONITORING bit = 0x1), the WAIT-invalid timing window is defined by the WRACCESSTIME field. WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before WRACCESSTIME completes. The advance pipelining of the two GPMC clock cycles is the result of the internal synchronization requirements for the WAIT signal. • WAIT monitored as active freezes the CYCLETIME counter. This informs the GPMC that the data bus is not captured by the external device. The control signals are kept in their current state. The data bus still drives the data. • WAIT monitored as inactive unfreezes the CYCLETIME counter. This informs that the data bus is correctly captured by the external device. All signals, including the data bus, are controlled according to their related control timing value and to the CYCLETIME counter status. When a delay larger than two GPMC clock cycles must be observed between wait-pin deassertion time and the effective data write into the external device (including the required GPMC data setup time and the device data setup time), an extra delay can be added between wait-pin deassertion time detection and effective data write time into the external device and the effective unfreezing of the CYCLETIME counter. This extra delay can be programmed in the GPMC.GPMC_CONFIG1_i[19:18] WAITMONITORINGTIME fields (i = 0 to 7). NOTE: • The WAITMONITORINGTIME parameter does not delay the wait-pin assertion or deassertion detection, nor does it modify the two GPMC clock cycles pipelined detection delay. • This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as synchronous, and even though no clock is provided to the external device. Still, GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER is used as a divider for the GPMC clock and so it must be programmed to define the correct WAITMONITORINGTIME delay. 10.1.5.4.3 Wait Monitoring During a Synchronous Read Access During synchronous accesses with wait-pin monitoring enabled, the wait pin is captured synchronously with GPMC_CLK, using the rising edge of this clock. The WAIT signal can be programmed to apply to the same clock cycle it is captured in. Alternatively, it can be sampled one or two GPMC_CLK cycles ahead of the clock cycle it applies to. This pipelining is applicable to the entire burst access, and to all data phase in the burst access. This WAIT pipelining depth is programmed in the GPMC.GPMC_CONFIG1_i[19:18] WAITMONITORINGTIME field (where i = 0 to 7), and is expressed as a number of GPMC_CLK clock cycles. In synchronous mode, when wait-pin monitoring is enabled (GPMC.GPMC_CONFIG1_i[22] WAITREADMONITORING bit), the effective access time is a logical AND combination of the RDACCESSTIME timing completion and the WAIT deasserted-state detection. Depending on the programmed WAITMONITORINGTIME value, the wait pin should be at a valid level, either asserted or deasserted: • In the same clock cycle the data is valid if WAITMONITORINGTIME = 0 ( at RDACCESSTIME completion) • In the WAITMONITORINGTIME * (GPMCFCLKDIVIDER + 1) GPMC_FCLK clock cycles before RDACCESSTIME completion if WAITMONITORINGTIME =/ 0 Similarly, during a multiple-access cycle (burst mode), the effective access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the wait-inactive state. The Wait pipelining depth programming applies to the whole burst access. • WAIT monitored as active freezes the CYCLETIME counter. For an access within a burst (when the CYCLETIME counter is by definition in a lock state), WAIT monitored as active extends the current access time in the burst. Control signals are kept in their current state. The data bus is considered invalid, and no data are captured during this clock cycle. 2118 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpmc_d[15:0] nBE1/nBE0 nCS nADV nOE DIR WAIT CLKACTIVATIONTIME CSONTIME ADVRDOFFTIME ADVONTIME OEONTIME RDCYCLETIME0 RDACCESSTIME Valid Address OEOFFTIME0 D0 D1 D2 D3 CSRDOFFTIME0 CSRDOFFTIME1 OEOFFTIME1 OUT IN OUT Wait de-asserted one GPMC.CLK cycle before valid data Public Version www.ti.com General-Purpose Memory Controller • WAIT monitored as inactive unfreezes the CYCLETIME counter. For an access within a burst (when the CYCLETIME counter is by definition in lock state), WAIT monitored as inactive completes the current access time and starts the next access phase in the burst. The data bus is considered valid, and data are captured during this clock cycle. In a single access or if this was the last access in a multiple-access cycle, all signals are controlled according to their relative control timing value and the CYCLETIME counter status. Figure 10-9 shows wait behavior during a synchronous read burst access. Figure 10-9. Wait Behavior During a Synchronous Read Burst Access PAGEBURSTACCESSTIME WaitMonitoringTime = 01 Wait de-asserted same cycle as valid data PAGEBURSTACCESSTIME PAGEBURSTACCESSTIME WaitMonitoringTime = 00 NOTE: The WAIT signal is active low. WAITMONITORINGTIME = 00, 01. 10.1.5.4.4 Wait Monitoring During a Synchronous Write Access RDCYCLETIME1 During synchronous accesses with wait-pin monitoring enabled (the WAITWRITEMONITORING bit), the wait pin is captured synchronously with GPMC_CLK, using the rising edge of this clock. If enabled, external wait-pin monitoring can be used in combination with WRACCESSTIME to control the effective memory device GPMC_CLK capture edge. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated gpmc-009 2119
Page 1 and 2: This chapter describes the memory s
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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