Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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512 Bytes input<br />
Row 0<br />
Row 1<br />
Row 2<br />
Row 3<br />
Row 508<br />
Row 509<br />
Row 5<strong>10</strong><br />
Row 511<br />
Public Version<br />
www.ti.com General-Purpose <strong>Memory</strong> Controller<br />
Figure <strong>10</strong>-29. ECC Computation for a 512-Byte Data Stream (Read or Write)<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0<br />
P1o P1e P1o P1e P1o P1e P1o P1e<br />
P2o P2e P2o P2e<br />
P4o P4e<br />
P8e<br />
P8o<br />
P8e<br />
P8o<br />
P8e<br />
P8o<br />
P8e<br />
P8o<br />
P16e<br />
P16o<br />
P16e<br />
P16o<br />
P2048e<br />
P2048o<br />
gpmc-029<br />
For a 2-Kbytes page, four 512-byte ECC calculations plus one for the spare area are required. Results are<br />
stored in the GPMC_ECCj_RESULT registers (j = 1 to 9).<br />
<strong>10</strong>.1.5.14.3.1.4 ECC Comparison and Correction<br />
To detect an error, the computed ECC result must be XORed with the parity value stored in the spare<br />
area of the accessed page.<br />
• If the result of this logical XOR is all 0s, no error is detected and the read data is correct.<br />
• If every second bit in the parity result is a 1, one bit is corrupted and is located at bit address (P2048o,<br />
P<strong>10</strong>24o, P512o, P256o, P128o, P64o, P32o, P16o, P8o, P4o, P2o, P1o). The software must correct<br />
the corresponding bit.<br />
• If only one bit in the parity result is 1, it is an ECC error and the read data is correct.<br />
<strong>10</strong>.1.5.14.3.1.5 ECC Calculation Based on 8-Bit Word<br />
The 8-bit based ECC computation is used for 8-bit wide NAND device interfacing.<br />
The 8-bit based ECC computation can be used for 16-bit wide NAND device interfacing to get backward<br />
compatibility on the error-handling strategy used with 8-bit wide NAND devices. In this case, the 16-bit<br />
wide data read from or written to the NAND device is fragmented into 2 bytes. According to little-endian<br />
access, the least significant bit (LSB) of the 16-bit wide data is ordered first in the byte stream used for<br />
8-bit based ECC computation.<br />
<strong>10</strong>.1.5.14.3.1.6 ECC Calculation Based on 16-Bit Word<br />
ECC computation based on a 16-bit word is used for 16-bit wide NAND device interfacing. This ECC<br />
computation is not supported when interfacing an 8-bit wide NAND device, and the<br />
GPMC.GPMC_ECC_CONFIG[7] ECC16B bit must be set to 0 when interfacing an 8-bit wide NAND<br />
device.<br />
The parity computation based on 16-bit words affects the row and column parity mapping. The main<br />
difference is that the odd and even parity bits P8o and P8e are computed on rows for an 8-bit based ECC<br />
while there are computed on columns for a 16-bit based ECC. Figure <strong>10</strong>-30 and Figure <strong>10</strong>-31 show a 128<br />
Word 16 ECC computation scheme and a 256 Word16 ECC computation scheme.<br />
SPRUGN4L–May 20<strong>10</strong>–Revised June 2011 <strong>Memory</strong> <strong>Subsystem</strong><br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
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