Chapter 10 Memory Subsystem.pdf

CLK_IN
SIGNAL_IN
MODEMAXDELAY
Initial delay
Phase
detector
Control
logic
C
D
L
Public Version
www.ti.com SDRAM Controller (SDRC) Subsystem
Figure 10-60. Simplified DLL/CDL Block Diagram
C
D
L
C
D
L
C
D
L
DCBFORCE
(8 bits)
+
DLL
DLL/CDL
C
D
L
SIGNAL_OUT
sdrc-017
The DLL circuit contains four delay elements in series. Therefore, the DLL output code and regulator
output voltage determine a delay equivalent to one fourth of the reference input period in a stand-alone
DLL/CDL (those CDLs are delay elements integrated into the DLL and are not shown in Figure 10-59). In
other words, the DLL/CDL delay is equivalent to 90 degrees without DLL/DCDL.
10.2.4.5 Mode Registers
10.2.4.5.1 Mode Register (MR)
This register is common to all SDR and DDR SDRAMs. It is a 12-bit register and controls the following
parameters:
• Write burst mode (SDRC.SDRC_MR_p[9] WBST bit (where p = 0 or 1 for SDRC CS0 or CS1)
• CAS latency (SDRC.SDRC_MR_p[6:4] CASL field)
• Serial/interleaved mode (SDRC.SDRC_MR_p[3] SIL bit)
• Burst length (SDRC.SDRC_MR_p[2:0] BL field)
MR is accessible through SDRC.SDRC_MR_p (where p = 0 or 1 for SDRC CS0 or CS1). Writing to
SDRC.SDRC_MR_p initiates an implicit load mode register command qualified by BA1, BA0 = 0, 0.
10.2.4.5.2 Extended Mode Register 2 (EMR2)
This register is specific to low-power SDR and mobile DDR SDRAM devices. It is a 12-bit register and
controls the following parameters:
• Temperature-compensated self-refresh (SDRC.SDRC_EMR2_p[4:3] TCSR field)
• Partial array self-refresh (SDRC.SDRC_EMR2_p[2:0] PASR field)
EMR2 is accessible through SDRC.SDRC_EMR2_p (where p stands for CS0 or CS1). Writing to
SDRC.SDRC_EMR2_p initiates an implicit load mode register command qualified by BA1, BA0 = 1, 0.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
Copyright © 2010–2011, Texas Instruments Incorporated
2245