Chapter 10 Memory Subsystem.pdf

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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (connected to A [26:17] on memory side) gpmc_d[15:0] (connected to A [16:1] / D [15:0] on memory side) nBE1/nBE0 nCS nADV nWE DIR WAIT CSONTIME Valid Address WRDATAONADMUXBUS Valid Address Data CSWROFFTIME ADVWROFFTIME ADVONTIME WEOFFTIME WEONTIME Public Version General-Purpose Memory Controller www.ti.com • Total access time (GPMC.GPMC_CONFIG5_i[4:0] RDCYCLETIME) corresponds to RDACCESSTIME plus the address hold time from nCS deassertion, plus time from RDACCESSTIME to CSWROFFTIME. • Direction signal DIR: DIR goes from OUT to IN at the same time as nOE assertion. After a read operation, if no other access (read or write) is pending, the data bus is driven with the previous read value. See Section 10.1.5.3.10, Bus Keeping Support. 10.1.5.10.2 Synchronous Single Write Figure 10-17. Synchronous Single Write on an Address/Data-Multiplexed Device NOTE: The WAIT signal is active low. WRCYCLETIME When the GPMC generates a write access to an address/data-multiplexed device, it drives the data bus until WRDATAONADMUXBUS time (GPMC_CONFIG6_i[19:16]). The GPMC.GPMC_CONFIG1_i register settings (i = 0 to 7) are as follows: OUT • WRITEMULTIPLE bit at 0 (write single access) • WRITETYPE bit at 1 (write synchronous) • MUXADDDATA bit at 1 (address/data-multiplexed device) Address bits [16:1] are placed on the address/data bus at cycle-start time, and the remaining address bits [26:17] are placed on the address bus. The address phase ends at WRDATAONADMUXBUS. The nCS, nADV, and nWE signals are controlled in the same way as nonmultiplexed accesses. First data of the burst is driven on the address/data bus at WRDATAONADMUXBUS time. 2132 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated gpmc-017
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (connected to A [9:0] on memory side) gpmc_d[15:0] (connected to D [15:0] on memory side) nBE1/nBE0 nCS nADV nOE DIR WAIT CLKACTIVATIONTIME CSONTIME ADVONTIME Valid Address ADVRDOFFTIME OEONTIME Valid Address Public Version www.ti.com General-Purpose Memory Controller 10.1.5.10.3 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability) Figure 10-18 and Figure 10-19 show a synchronous multiple read operation with GPMCFCLKDivider equal to 0 and 1, respectively. Figure 10-18. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) NOTE: The WAIT signal is active low. RDCYCLETIME0 RDACCESSTIME CSRDOFFTIME0 OEOFFTIME PAGEBURSTACCESSTIME PAGEBURSTACCESSTIME D0 D1 D2 D3 RDCYCLETIME1 PAGEBURSTACCESSTIME CSRDOFFTIME1 OUT IN OUT SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated gpmc-018 2133
Page 1 and 2: This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
Page 5 and 6: Public Version www.ti.com General-P
Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 37: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76: Device GPMC module A [27:17] A [16:
Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
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Public Version www.ti.com General-P
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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