Chapter 10 Memory Subsystem.pdf

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10.1.3.2 Clocking, Reset, and Power-Management Scheme
10.1.3.2.1 Clocking
The GPMC use a single clock, GPMC_FCLK, which comes internally from the power, reset, and
clock-management (PRCM) module and runs at the L3 interconnect frequency. Its source is the PRCM
module, CORE_L3_ICLK output. CORE_L3_ICLK belongs to the L3 interconnect clock domain.
For details, see Chapter 3, Power, Reset, and Clock Management .
GPMC_CLK is the external clock provided to the attached synchronous memory or device. The
GPMC_CLK clock frequency is the GPMC_FCLK clock frequency divided by 1, 2, 3, or 4, depending on
the GPMC.GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER bit field (where i = 0 to 7).
NOTE: When the GPMC is configured for synchronous mode, the GPMC_CLK signal (which is an
output) must also be set as an input (CONTROL.CONTROL_PADCONF_GPMC_NCS7[24]
INPUTENABLE1 = 1). GPMC_CLK is looped back through the output and input buffers of
the corresponding GPMC_CLK pad at the device boundary. The looped-back clock is used
to synchronize the sampling of the memory signals.
10.1.3.2.2 Hardware Reset
A global reset of the GPMC occurs through activation of the CORE_RSTRET signal (CORE power
domain) controlled by the PRCM module (see Chapter 3 , Power, Reset, and Clock Management ).
The CORE_RSTRET signal is activated during IC global power-on and global warm reset, and it resets
the controller state machine and configuration registers.
10.1.3.2.3 Software Reset
GPMC modules can be reset under software control through the GPMC.GPMC_SYSCONFIG[1]
SOFTRESET bit. When software reset bit is set, all registers and the finite state-machine (FSM) are reset
immediately and unconditionally. The GPMC_SYSSTATUS[0] RESETDONE bit can be polled to check
reset status.
10.1.3.2.4 Power Domain, Power Saving, and Reset Management
GPMC power is supplied by the CORE power domain, and GPMC power management complies with
system power-management guidelines.
The GPMC reduces power consumption through auto-idle mode and the idle request/acknowledge
process, both of which are configurable:
• Dynamic auto-idle (configurable through the GPMC.GPMC_SYSCONFIG[0] AUTOIDLE bit): To reduce
power consumption, the GPMC internally disables the functional clock when no requests are pending
and no accesses are ongoing.
• Idle request/acknowledge (one of three idle modes configurable through the
GPMC.GPMC_SYSCONFIG[4:3] IDLEMODE field):
– Force-idle: Immediately on receiving an idle request from the PRCM module, the GPMC sends an
idle request/acknowledge to let the PRCM module correctly cut the GPMC source clock.
– No-idle: The GPMC never goes to idle mode.
– Smart-idle (strongly recommended): The GPMC goes to idle mode when all ongoing transactions
are complete.
For detailed information about power management, see Chapter 3, Power, Reset, and Clock
Management.
10.1.3.2.5 Hardware Requests
The GPMC uses two hardware requests as shown in Figure 10-4 :
• One interrupt request goes from GPMC (GPMC_IRQ) to the microprocessor unit (MPU) subsystem :
M_IRQ_20.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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