Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Public Version General-Purpose Memory Controller www.ti.com Bits Field Name Description Type Reset 9 WAIT1STATUS Is a copy of input pin WAIT1. (Reset value is WAIT1 input R 0xpin sampled at IC reset) 0x0: WAIT1 asserted (inactive state) 0x1: WAIT1 de-asserted 8 WAIT0STATUS Is a copy of input pin WAIT0. (Reset value is WAIT0 input R 0xpin sampled at IC reset) 0x0: WAIT0 asserted (inactive state) 0x1: WAIT0 de-asserted 7:1 RESERVED Write 0s for future compatibility. Reads returns 0 RW 0x00 0 EMPTYWRITEBUFFERSTATUS Stores the empty status of the write buffer R 0x1 0x0: Write Buffer is not empty 0x1: Write Buffer is empty Table 10-48. Register Call Summary for Register GPMC_STATUS General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] • GPMC Register Summary: [4] Table 10-49. GPMC_CONFIG1_i Address Offset 0x0000 0060 + (0x0000 0030 * i) Index i = 0 to 7 Physical Address 0x6E00 0060 + (0x0000 0030 * i) Instance GPMC Description The configuration register 1 sets signal control parameters per chip-select Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRAPBURST READMULTIPLE READTYPE WRITEMULTIPLE WRITETYPE CLKACTIVATIONTIME ATTACHEDDEVICEPAGELENGTH WAITREADMONITORING WAITWRITEMONITORING RESERVED WAITMONITORINGTIME WAITPINSELECT RESERVED DEVICESIZE DEVICETYPE MUXADDDATA RESERVED Bits Field Name Description Type Reset 31 WRAPBURST Enables the wrapping burst capability. Must be set if the RW 0x0 attached device is configured in wrapping burst 0x0: Synchronous wrapping burst not supported 0x1: Synchronous wrapping burst supported 30 READMULTIPLE Selects the read single or multiple access RW 0x0 0x0: Single access 0x1: Multiple access (burst if synchronous, page if asynchronous) 29 READTYPE Selects the read mode operation RW 0x0 0x0: Read Asynchronous 0x1: Read Synchronous 2186 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated TIMEPARAGRANULARITY RESERVED GPMCFCLKDIVIDER
Public Version www.ti.com General-Purpose Memory Controller Bits Field Name Description Type Reset 28 WRITEMULTIPLE Selects the write single or multiple access RW 0x0 0x0: Single access 0x1: Multiple access (burst if synchronous, considered as single if asynchronous) 27 WRITETYPE Selects the write mode operation RW 0x0 0x0: Write Asynchronous 0x1: Write Synchronous 26:25 CLKACTIVATIONTIME Output GPMC_CLK activation time RW 0x0 0x0: First rising edge of GPMC_CLK at start access time 0x1: First rising edge of GPMC_CLK one GPMC_FCLK cycle after start access time 0x2: First rising edge of GPMC_CLK two GPMC_FCLK cycles after start access time 0x3: Reserved 24:23 ATTACHEDDEVICEPAGE Specifies the attached device page (burst) length RW 0x0 LENGTH 0x0: 4 Words 0x1: 8 Words 0x2: 16 Words 0x3: Reserved (1 Word = Interface size) 22 WAITREADMONITORING Selects the Wait monitoring configuration for Read accesses RW 0x- (Reset value is BOOTWAITEN input pin sampled at IC reset) 0x0: Wait pin is not monitored for read accesses 0x1: Wait pin is monitored for read accesses 21 WAITWRITEMONITORING Selects the Wait monitoring configuration for Write accesses RW 0x0 0x0: Wait pin is not monitored for write accesses 0x1: Wait pin is monitored for write accesses 20 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 19:18 WAITMONITORINGTIME Selects input pin Wait monitoring time RW 0x0 0x0: Wait pin is monitored with valid data 0x1: Wait pin is monitored one GPMC_CLK cycle before valid data 0x2: Wait pin is monitored two GPMC_CLK cycle before valid data 0x3: Reserved 17:16 WAITPINSELECT Selects the input WAIT pin for this chip-select (Reset value RW 0xis BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7) 0x0: Wait input pin is WAIT0 0x1: Wait input pin is WAIT1 0x2: Wait input pin is WAIT2 0x3: Wait input pin is WAIT3 15:14 RESERVED Write 0s for future compatibility. RW 0x0 Reads returns 0 13:12 DEVICESIZE Selects the device size attached (Reset value is RW 0x- BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 0x1 for CS1 to CS7) 0x0: 8 bit 0x1: 16 bit 0x2: Reserved 0x3: Reserved SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2187
Page 1 and 2:
This chapter describes the memory s
Page 3 and 4:
Device GPMC External device/ memory
Page 5 and 6:
Public Version www.ti.com General-P
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
1 GBytes 512 MBytes 256 MBytes 128
Page 15 and 16:
Page 17 and 18:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 45 and 46: Public Version www.ti.com General-P
Page 47 and 48: nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50: nCS nBE0/CLE nWE Public Version www
Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
Page 61 and 62: M0 Manual mode Rd/Wr/ SW Mode Size0
Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68: M9 Per-sector spares, separate ECC
Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76: Device GPMC module A [27:17] A [16:
Page 77 and 78: FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80: FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 91: Public Version www.ti.com General-P
Page 111 and 112: Public Version www.ti.com SDRAM Con
Page 115 and 116: Device SDRAM controller subsystem R
Page 119 and 120: MUX1 System address 31 30 29 28 27
Page 121 and 122: MUX23 System address Address mappin
Page 125 and 126: Configuration register file Rotatio
Page 131 and 132: Level 0 Region 0 Public Version www
Page 135 and 136: OCP slave interface OCP slave port
Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
Page 143 and 144:
Endianism CSnMUXCFG field SDRC.SDRC
Page 145 and 146:
Public Version www.ti.com SDRAM Con
Page 147 and 148:
Page 149 and 150:
CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152:
CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170:
Start configuration of VRFB context
Page 171 and 172:
Initiator: Camera subsystem SDRC Su
Page 173 and 174:
Page 175 and 176:
Request for transaction on class 1
Page 177 and 178:
Class 1 and class 2 request for tra
Page 179 and 180:
No A Class 0 empty? Yes Class 1 emp
Page 181 and 182:
Status: There are n pending request
Page 183 and 184:
4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222:
Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

Create successful ePaper yourself

Delete template?

Save as template?