Chapter 10 Memory Subsystem.pdf

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Public Version General-Purpose Memory Controller www.ti.com Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000 11:8 MASKADDRESS CS mask address. RW 0xF 0x0000: Chip-select size of 256 Mbytes 0x1000: Chip-select size of 128 Mbytes 0x1100: Chip-select size of 64 Mbytes 0x1110: Chip-select size of 32 Mbytes 0x1111: Chip-select size of 16 Mbytes Other values must be avoided as they create holes in the chip-select address space. 7 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 6 CSVALID CS enable RW See (1) 0x0: CS disabled 0x1: CS enabled 5:0 BASEADDRESS CSi base address (16M bytes minimum granularity) bits [5:0] RW 0x00 corresponds to A29, A28, A27, A26, A25, and A24. See Figure 10-6 (1) Reset value is 0x1 for CS0 and 0x0 for CS1 to CS7 Table 10-62. Register Call Summary for Register GPMC_CONFIG7_i General-Purpose Memory Controller • Chip-Select Base Address and Region Size Configuration: [0] [1] [2] • NAND Device Basic Programming Model: [3] • GPMC Register Summary: [4] Table 10-63. GPMC_NAND_COMMAND_i Address Offset 0x0000 007C + (0x0000 0030 * i) Index i = 0 to 7 Physical Address 0x6E00 007C + (0x0000 0030 * i) Instance GPMC Description This register is not a true register, just an address location. Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPMC_NAND_COMMAND Bits Field Name Description Type Reset 31:0 GPMC_NAND_COMMAND This register is not a true register, just an address W n/a location. Table 10-64. Register Call Summary for Register GPMC_NAND_COMMAND_i General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] [6] • GPMC Register Summary: [7] Table 10-65. GPMC_NAND_ADDRESS_i Address Offset 0x0000 0080 + (0x0000 0030 * i) Index i = 0 to 7 Physical Address 0x6E00 0080 + (0x0000 0030 * i) Instance GPMC Description This register is not a true register, just an address location. Type W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPMC_NAND_ADDRESS 2194 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com General-Purpose Memory Controller Bits Field Name Description Type Reset 31:0 GPMC_NAND_ADDRESS This register is not a true register, just an address W n/a location. Table 10-66. Register Call Summary for Register GPMC_NAND_ADDRESS_i General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] [6] • GPMC Register Summary: [7] Table 10-67. GPMC_NAND_DATA_i Address Offset 0x0000 0084 + (0x0000 0030 * i) Index i = 0 to 7 Physical Address 0x6E00 0084 + (0x0000 0030 * i) Instance GPMC Description This register is not a true register, just an address location. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPMC_NAND_DATA Bits Field Name Description Type Reset 31:0 GPMC_NAND_DATA This register is not a true register, just an address location. W n/a Table 10-68. Register Call Summary for Register GPMC_NAND_DATA_i General-Purpose Memory Controller • NAND Device Basic Programming Model: [0] [1] [2] [3] [4] [5] • GPMC Register Summary: [6] • GPMC Register Description: [7] [8] Address Offset 0x0000 01E0 Table 10-69. GPMC_PREFETCH_CONFIG1 Physical Address 0x6E00 01E0 Instance GPMC Description Prefetch engine configuration 1 Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CYCLEOPTIMIZATION ENABLEOPTIMIZEDACCESS ENGINECSSELECTOR PFPWENROUNDROBIN RESERVED PFPWWEIGHTEDPRIO RESERVED FIFOTHRESHOLD SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated ENABLEENGINE RESERVED WAITPINSELECTOR SYNCHROMODE DMAMODE RESERVED ACCESSMODE 2195
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
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Page 67 and 68: M9 Per-sector spares, separate ECC
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Public Version www.ti.com SDRAM Con
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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