Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com 10.2.4.4.11 Controlled Delay Line The DLL/CDL module is a hard macro composed of one master delay-locked loop (DLL) and five slave-controlled delay lines (CDL). It is used to generate precise delays suitable for DDR read and write operations. DLL delays are tracked at high frequency on process dispersion, and voltage and temperature variations (PVT) . A CDL is a component with a clock input signal, a clock output signal, and a delay value input. The output signal is the input signal delayed according to the delay value. The DLL output is a command that controls the CDLs (plus the controlled voltage) and assures an output signal with 90-degree delay with respect to its input signal. The DLL contains five CDL blocks. 10.2.4.4.11.1 Purpose of the DLL/CDL Module In DDR applications, the DLL and CDL combination helps provide a data strobe (DQS) with a delay suitable to the main read and write RAM operations that exceed 83 MHz. The DLL functions within a locking range of 83 to 200 Mhz. Below 83 MHz, the DLL must be used in unlocked mode. For lower clock frequencies, set the DLL to bypass mode. DLL/CDL is used to delay the incoming DQS in case of DDR read, or delay the output DQ (data lines) in case of DDR write (and, hence, to increase the ac timing margin). DQS is used only with DDR memory. There is no need to use the DLL/CDL for the SDR DRAM because data is strobed every clock cycle. The DQS signals are left unconnected for SDR SDRAM memories. DQS is propagated with the data (thus reducing the impact of the propagation delay) and is used by the receiver to sample the data. The DLL/CDL combination minimizes the negative effects caused by skews and jitters of clock signals. The delay introduced by the CDL base unit depends on PVT conditions. Moreover, the CDL timing delay is not a linear function of the DLL counter offset. By means of the DLL feedback loop, the delay value is updated in real time and is adjusted according to voltage and temperature variations. DDR interfaces transmit data on both edges of the DQS bidirectional data strobe. Address and control signals transmit at half the data frequency (that is, at the DDR clock frequency) and latch only on the rising edge of the transmit clock. The bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. sdrc_dqs[3:0] is an SDRC I/O that connects the SDRC with DDR SDRAM DQS pins. See Figure 10-43 for an overview of DDR SDRAM connection with the SDRC. DQS is transmitted by the DDR SDRAM during reads and by the SDRC during writes. DQS is edge-aligned with data for reads and center-aligned with data for writes, as shown in Figure 10-57. Figure 10-57 shows the generic DDR data-write and data-read waveforms. 2242 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
CLK CMD WRITE DQ DQS CLK CMD DQ DQS DQ DQS DQ DQS READ Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Figure 10-57. Generic DDR Data-Write and Data-Read Waveforms DDR data-write CAS latency DDR data-read Figure 10-58 shows the DDR SDRAM data and data strobe DQS signals exiting synchronously and in phase during a data read. DQS signals are used to sample incoming data internally and, hence, must be delayed to create data-setup and data-hold time at the synchronization flip-flop inputs, as shown in the bottom waveforms of Figure 10-58. This is the goal of the DLL/CDL module. 10.2.4.4.11.2 DLL/CDL Module Architecture Figure 10-58. Required Synchronization DFF Input Signals Data and data strobe from DDR-SDRAM Data strobe is internally delayed to respect data setup and hold time Figure 10-59 shows how the DLL/CDL interacts with the synchronization flip-flops. See Table 10-102 for more information on device pins and SDRC data-lane configurations regarding DQS. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated sdrc-014 sdrc-015 2243
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This chapter describes the memory s
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Device GPMC External device/ memory
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Device D2D OCM_ROM OCM_RAM ROM (32K
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