Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
Table 10-15. Prefetch Mode Configuration (continued)
Bit Field Register Value Comments
SYNCHROMODE GPMC_PREFETCH_CONFIG1[3] 0/1 Selects when the engine starts the access to
the chip-select
WAITPINSELECT GPMC_PREFETCH_CONFIG1[17:16] 0 to 3 (If SynchroMode = 1) Selects wait pin edge
detector
ENABLEOPTIMIZEDACCESS GPMC_PREFETCH_CONFIG1[27] 0/1 See Section 10.1.5.14.4.6.
CYCLEOPTIMIZATION GPMC_PREFETCH_CONFIG1[30:28]
ENABLEENGINE GPMC_PREFETCH_CONFIG1[7] 1 Engine enabled
STARTENGINE GPMC_PREFETCH_CONTROL[0] 1 Starts the prefetch engine
10.1.5.14.4.3 FIFO Control in Prefetch Mode
The FIFO can be drained directly by the MPU or by an sDMA channel.
In MPU draining mode, the FIFO status can be monitored through the
GPMC.GPMC_PREFETCH_STATUS[30:24] FIFOPOINTER field or through the
GPMC.GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bit. The FIFOPOINTER indicates
the current number of available data to be read; FIFOTHRESHOLDSTATUS set to 1 indicates that at least
FIFOTHRESHOLD bytes are available from the FIFO.
An interrupt can be triggered by the GPMC if the GPMC.GPMC_IRQENABLE[0] FIFOEVENTENABLE bit
is set. The FIFO interrupt event is logged, and the GPMC.GPMC_IRQSTATUS[0] FIFOEVENTSTATUS bit
is set. To clear the interrupt, the MPU must read all the available bytes, or at least enough bytes to get
below the programmed FIFO threshold, and the FIFOEVENTSTATUS bit must be cleared to enable
further interrupt events. The FIFOEVENTSTATUS bit must always be reset prior to asserting the
FIFOEVENTENABLE bit to clear any out-of-date logged interrupt event. This interrupt generation must be
enabled after enabling the STARTENGINE bit.
Prefetch completion can be monitored through the GPMC.GPMC_PREFETCH_STATUS[13:0]
COUNTVALUE field. COUNTVALUE indicates the number of currently remaining data to be requested
according to the TRANSFERCOUNT value. An interrupt can be triggered by the GPMC when the prefetch
process is complete (that is, COUNTVALUE equals 0) if the GPMC.GPMC_IRQENABLE[1]
TERMINALCOUNTEVENTENABLE bit is set. At prefetch completion, thehe TERMINALCOUNT interrupt
event is also logged, and the GPMC.GPMC_IRQSTATUS[1] TERMINALCOUNTSTATUS bit is set. To
clear the interrupt, the MPU must clear the TERMINALCOUNTSTATUS bit. The
TERMINALCOUNTSTATUS bit must always be cleared prior to asserting the
TERMINALCOUNTEVENTENABLE bit to clear any out-of-date logged interrupt event.
NOTE: The COUNTVALUE value is only valid when the prefetch engine is active (started), and an
interrupt is triggered only when COUNTVALUE reaches 0 (that is, when the prefetch engine
automatically goes from an active to inactive state).
The number of bytes to be prefetched (programmed in TRANSFERCOUNT) must be a multiple of the
programmed FIFOTHRESHOLD to trigger the correct number of interrupts allowing a deterministic and
transparent FIFO control. If this guideline is respected, the number of ISR accesses is always required
and the FIFO is always empty after the last interrupt is trigerred. In other cases, the TERMINALCOUNT
interrupt must be used to read the remaining bytes in the FIFO (the number of remaining bytes being
lower than the FIFOTHRESHOLD value).
In DMA draining mode, the GPMC.GPMC_PREFETCH_CONFIG1[2] DMAMODE bit must be set so that
the GPMC issues a DMA hardware request when at least FIFOTHRESHOLD bytes are ready to be read
from the FIFO. The DMA channel owning this DMA request must be programmed so that the number of
bytes programmed in FIFOTHRESHOLD is read from the FIFO during the DMA request process. The
DMA request is kept active until this number of bytes has effectively been read from the FIFO, and no
other DMA request can be issued until the ongoing active request is complete.
2164 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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