Chapter 10 Memory Subsystem.pdf

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Table 10-184. Register Call Summary for Register SDRC_RFR_CTRL_p
SDRAM Controller (SDRC) Subsystem
• Autorefresh Management: [0] [1] [2]
• Memory Power Management: [3] [4] [5]
• SDRC Register Summary: [6]
Table 10-185. SDRC_MANUAL_p
Address Offset 0x0000 00A8 + (0x0000 0030 * p) Index p = 0 to 1
Physical Address 0x6D00 00A8 + (0x0000 0030 * p) Instance SDRC
Description This register allows to send specific commands to the external memory devices under software control. Any write
to this register generates the appropriate sequence based on the command code.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDPARAM RESERVED CMDCODE
Bits Field Name Description Type Reset
31:16 CMDPARAM Manual command parameter, if any. RW 0x0000
15:4 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000
3:0 CMDCODE Memory command opcode; other values reserved for future RW 0x0
implementations.
0x0: NOP command - no parameter
0x1: Precharge all command - no parameter
0x2: Autorefresh command - no parameter
0x3: Enter deep-power-down - no parameter
0x4: Exit deep-power-down - no parameter
0x5: Enter self-refresh - no parameter
0x6: Exit self-refresh - no parameter
0x7: Set CKE signal high - no parameter
0x8: Set CKE low - no parameter
0x9: Reserved
0xA: Reserved
0xB: Reserved
0xC: Reserved
Table 10-186. Register Call Summary for Register SDRC_MANUAL_p
SDRAM Controller (SDRC) Subsystem
• Refresh Management: [0]
• Power-Saving Features: [1]
• SDRC Power-Down Mode: [2]
• Autorefresh Management: [3]
• Manual Software Commands: [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
• Low-Power SDR/Mobile DDR Initialization Sequence: [14]
• Memory Power Management: [15]
• SDRC Register Summary: [16]
2312 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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