Chapter 10 Memory Subsystem.pdf

More documents

Recommendations

Info

Public Version SDRAM Controller (SDRC) Subsystem www.ti.com 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED AUTOCOUNT WAKEUPPROC RESERVED Bits Field Name Description Type Reset 31:27 RESERVED Write 0s for future compatibility. RW 0x00 Read returns 0. 26 WAKEUPPROC Select if after a SDRC wakeup in DDR mode (in DLL tracking-delay RW 0x0 mode), the first request is stalled during 500 cycles latency or until the lock signal from the DLL/CDL analog cell is asserted. 0x0: SDRC allows DDR access after 500 L3 clock cycles. 0x1: SDRC allows DDR access as soon as DLL LOCKSTATUS bit is 1. 25:24 RESERVED Write 0s for future compatibility. RW 0x0 Read returns 0. 23:8 AUTOCOUNT 16-bit programmable count value used for delayed automatic clock RW 0x0000 gating and self-refresh entry, assuming CLKCTRL field is not 0 7 SRFRONRESET Enter self refresh when a warm reset is applied: RW 0x1 0x0: Feature disabled 0x1: Feature enabled 6 SRFRONIDLEREQ Enter self refresh when on hardware idle request: RW 0x0 0x0: Feature disabled 0x1: Feature enabled 5:4 CLKCTRL Clock control feature defines clock gating and self refresh: RW 0x0 0x0: No auto clk feature turned on 0x1: Enable internal clock gating on timeout of Auto_cnt 0x2: Enable self-refresh on timeout of Auto_cnt 0x3: Reserved 3 EXTCLKDIS Disable the clock provided to the external memories: RW 0x0 0x0: Enable clock 0x1: Disable clock- Logical 0 is applied. 2 PWDENA Activate the power-down mode of the target memory through CKE pin. RW 0x1 0x0: Power-down mode feature disabled 0x1: Power-down mode feature enabled 1 RESERVED Write 0 for future compatibility. Read returns 0. RW 0x0 0 PAGEPOLICY Page/segment closure policy with respect to power versus bandwidth RW 0x1 trade-off - Must be set to 1 0x0: Reserved - must not be used 0x1: High-power/high bandwidth mode (HPHB) Table 10-172. Register Call Summary for Register SDRC_POWER_REG SDRAM Controller (SDRC) Subsystem • Hardware Reset: [0] • Power Management: [1] • Refresh Management: [2] • Power-Saving Features: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] • Reset Behavior: [15] [16] • Page Closure Strategy: [17] • Memory Power Management: [18] [19] [20] • SDRC Register Summary: [21] 2304Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated SRFRONRESET SRFRONIDLEREQ CLKCTRL EXTCLKDIS PWDENA RESERVED PAGEPOLICY
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-173. SDRC_MCFG_p Address Offset 0x0000 0080 + (0x0000 0030 * p) Index p = 0 to 1 Physical Address 0x6D00 0080 + (0x0000 0030 * p) Instance SDRC Description This register provides the memory configuration register. Type RW Register Description for ADDRMUXLEGACY = 0x1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED LOCKSTATUS RESERVED RASWIDTH RESERVED CASWIDTH ADDRMUXLEGACY RESERVED RAMSIZE Bits Field Name Description Type Reset 31 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0 30 LOCKSTATUS Read-only access lock bit RW See (1) 0x0: This register is fully writable 0x1: When this bit is set, the register can not be unset until next reset of the module. 29:27 RESERVED Write 0s for future compatibility. Read returns 0. RW See (1) 26:24 RASWIDTH RAS address width RW See (1) 0x0: RAS width = 11 bits 0x1: RAS width = 12 bits 0x2: RAS width = 13 bits 0x3: RAS width = 14 bits 0x4: RAS width = 15 bits 0x5: RAS width = 16 bits - Must not be used 0x6: RAS width = 17 bits - Must not be used 0x7: RAS width = 18 bits - Must not be used 23 RESERVED Write 0s for future compatibility. Read returns 0. RW See (1) 22:20 CASWIDTH CAS address width RW See (1) 0x0: CAS width = 5 bits 0x1: CAS width = 6 bits 0x2: CAS width = 7 bits 0x3: CAS width = 8 bits 0x4: CAS width = 9 bits 0x5: CAS width = 10 bits 0x6: CAS width = 11 bits 0x7: CAS width = 12 bits 19 ADDRMUXLEGACY Selects the fixed address-muxing scheme or the flexible address-muxing RW See (1) scheme 0x0: Fixed address mux scheme 0x1: Flexible address mux scheme 18 RESERVED Write 0s for future compatibility. Read returns 0. RW See (1) 17:8 RAMSIZE RAM address space size number of 2-MB chunks RW See (1) (1) Reset value is copied from the system control module. See the note in Section 10.2.5.3.2 and Section 13.4.9, SDRC Registers, in Chapter 13, System Control Module. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated BANKALLOCATION RESERVED B32NOT16 DEEPPD DDRTYPE RAMTYPE 2305
Page 1 and 2:
This chapter describes the memory s
Page 3 and 4:
Device GPMC External device/ memory
Page 5 and 6:
Public Version www.ti.com General-P
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
1 GBytes 512 MBytes 256 MBytes 128
Page 15 and 16:
Page 17 and 18:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
Page 45 and 46:
Page 47 and 48:
nCS nBE0/CLE nWE nADV/ALE CSONTIME=
Page 49 and 50:
nCS nBE0/CLE nWE Public Version www
Page 51 and 52:
Page 53 and 54:
Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56:
512 Bytes input Row 0 Row 1 Row 2 R
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
M0 Manual mode Rd/Wr/ SW Mode Size0
Page 63 and 64:
Page 65 and 66:
M1 M2 M3 M4 Per-sector spares Spare
Page 67 and 68:
M9 Per-sector spares, separate ECC
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
Page 75 and 76:
Device GPMC module A [27:17] A [16:
Page 77 and 78:
FCLK CLK nADV nCS nOE A/D bus ClkAc
Page 79 and 80:
FCLK nCS nADV nWE A/D bus AdvWrOffT
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Public Version www.ti.com SDRAM Con
Page 113 and 114:
Page 115 and 116:
Device SDRAM controller subsystem R
Page 117 and 118:
Page 119 and 120:
MUX1 System address 31 30 29 28 27
Page 121 and 122:
MUX23 System address Address mappin
Page 123 and 124:
Page 125 and 126:
Configuration register file Rotatio
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Level 0 Region 0 Public Version www
Page 133 and 134:
Page 135 and 136:
OCP slave interface OCP slave port
Page 137 and 138:
Page 139 and 140:
BANKALLOCATION = 0b00 BANKALLOCATIO
Page 141 and 142:
Page 143 and 144:
Endianism CSnMUXCFG field SDRC.SDRC
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
CLK CMD WRITE DQ DQS CLK CMD DQ DQS
Page 151 and 152:
CLK_IN SIGNAL_IN MODEMAXDELAY Initi
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160: Public Version www.ti.com SDRAM Con
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
Page 169 and 170: Start configuration of VRFB context
Page 171 and 172: Initiator: Camera subsystem SDRC Su
Page 175 and 176: Request for transaction on class 1
Page 177 and 178: Class 1 and class 2 request for tra
Page 179 and 180: No A Class 0 empty? Yes Class 1 emp
Page 181 and 182: Status: There are n pending request
Page 183 and 184: 4 GB 0x0000 0000 0x6C00 0000 0x6CFF
Page 209: Public Version www.ti.com SDRAM Con
Page 219 and 220: Device D2D OCM_ROM OCM_RAM ROM (32K
Page 221 and 222: Public Version www.ti.com On-Chip M
show all

Chapter 10 Memory Subsystem.pdf

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?