Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
Chapter 10 Memory Subsystem.pdf
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Public Version<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong> www.ti.com<br />
Address Offset 0x0000 0178<br />
Table <strong>10</strong>-143. SMS_POW_CTRL<br />
Physical Address 0x6C00 0178 Instance SMS<br />
Description This register controls the SMS power management in conjunction with the regular interconnect socket<br />
registers.<br />
Type RW<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
RESERVED IDLEDELAY<br />
Bits Field Name Description Type Reset<br />
31:8 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000<br />
7:0 IDLEDELAY Delay (expressed in L3 clock cycle units) before autoidle, that is, RW 0x80<br />
before disabling the SMS functional clock when no more traffic in the<br />
SMS module.<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
• Module Power Saving: [0]<br />
• SMS Register Summary: [1]<br />
Table <strong>10</strong>-144. Register Call Summary for Register SMS_POW_CTRL<br />
Table <strong>10</strong>-145. SMS_ROT_CONTROLn<br />
Address Offset 0x0000 0180 + (0x0000 00<strong>10</strong> * n) Index n = 0 to 11<br />
Physical Address 0x6C00 0180 + (0x0000 00<strong>10</strong> * n) Instance SMS<br />
Description This register configures the virtual rotated frame buffer module for context #n.<br />
Type RW<br />
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 <strong>10</strong> 9 8 7 6 5 4 3 2 1 0<br />
RESERVED PH PW PS<br />
Bits Field Name Description Type Reset<br />
31:11 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x000000<br />
<strong>10</strong>:8 PH Exponent based 2 value, 2 ph indicates the page height in bytes for context RW 0x0<br />
#n.<br />
7 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0<br />
6:4 PW Exponent based 2 value, 2 pw indicates the page width in bytes for context RW 0x0<br />
#n.<br />
3:2 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x0<br />
1:0 PS Exponent based 2 value, 2 ps indicates the pixel size in bytes for context RW 0x0<br />
#n. A value of 3 is invalid.<br />
Table <strong>10</strong>-146. Register Call Summary for Register SMS_ROT_CONTROLn<br />
SDRAM Controller (SDRC) <strong>Subsystem</strong><br />
• Rotation Engine: [0] [1]<br />
• VRFB Context Configuration: [2] [3] [4]<br />
• Applicative Use Case and Tips: [5] [6] [7]<br />
• SMS Register Summary: [8]<br />
2294<strong>Memory</strong> <strong>Subsystem</strong> SPRUGN4L–May 20<strong>10</strong>–Revised June 2011<br />
Copyright © 20<strong>10</strong>–2011, Texas Instruments Incorporated<br />
RESERVED<br />
RESERVED