Chapter 10 Memory Subsystem.pdf

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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (connected to A[9:0] on memory side) gpmc_d[15:0] (connected to D[15:0] on memory side) nBE1/nBE0 nCS nADV nOE WAIT CLKACTIVATIONTIME CSONTIME ADVRDOFFTIME ADVONTIME OEONTIME RDCYCLETIME RDACCESSTIME CSRDOFFTIME OEOFFTIME Public Version General-Purpose Memory Controller www.ti.com Figure 10-15. Synchronous Single Read (GPMCFCLKDIVIDER = 0) Valid Address 2130 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 D 0 Copyright © 2010–2011, Texas Instruments Incorporated gpmc-015
GPMC_FCLK GPMC_CLK gpmc_a[11:1] (connected to A[9:0] on memory side) gpmc_d[15:0] (connected to D[15:0] on memory side) nBE1/nBE0 nCS nADV nOE WAIT CLKACTIVATIONTIME CSONTIME ADVRDOFFTIME ADVONTIME OEONTIME CSRDOFFTIME OEOFFTIME RDCYCLETIME Public Version www.ti.com General-Purpose Memory Controller Figure 10-16. Synchronous Single Read (GPMCFCLKDIVIDER = 1) RDACCESSTIME Valid Address In the following section i stands for the chip-select number, i = 0 to 7. • GPMC.GPMC_CONFIG1_i register settings: – READMULTIPLE bit at 0 (read single access) – READTYPE bit at 1 (read synchronous) – MUXADDDATA bit at 0 (non-address/data-multiplexed device) • Chip-select signal nCS: – nCS assertion time is controlled by the GPMC.GPMC_CONFIG2_i[3:0] CSONTIME field and ensures address setup time to nCS assertion. – nCS deassertion time is controlled by the GPMC.GPMC_CONFIG2_i[12:8] CSRDOFFTIME field and ensures address hold time to nCS deassertion. • Address valid signal nADV: – nADV assertion time is controlled by the GPMC.GPMC_CONFIG3_i[3:0] ADVONTIME field. – nADV deassertion time is controlled by the GPMC.GPMC_CONFIG3_i[12:8] ADVRDOFFTIME field. • Output enable signal nOE: – nOE assertion indicates a read cycle. – nOE assertion time is controlled by the GPMC.GPMC_CONFIG4_i[3:0] OEONTIME field. – nOE deassertion time is controlled by the GPMC.GPMC_CONFIG4_i[12:8] OEOFFTIME field. • Initial latency for the first read data is controlled by GPMC.GPMC_CONFIG5_i[20:16] RDACCESSTIME or by monitoring the WAIT signal. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem D 0 Copyright © 2010–2011, Texas Instruments Incorporated gpmc-016 2131
Page 1 and 2: This chapter describes the memory s
Page 3 and 4: Device GPMC External device/ memory
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Page 13 and 14: 1 GBytes 512 MBytes 256 MBytes 128
Page 17 and 18: GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
Page 25 and 26: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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Page 43 and 44: GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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Page 53 and 54: Row 0 Row 1 Row 2 Row 3 Row 252 Row
Page 55 and 56: 512 Bytes input Row 0 Row 1 Row 2 R
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Page 65 and 66: M1 M2 M3 M4 Per-sector spares Spare
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Page 73 and 74: GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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Start configuration of VRFB context
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Initiator: Camera subsystem SDRC Su
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Request for transaction on class 1
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Class 1 and class 2 request for tra
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No A Class 0 empty? Yes Class 1 emp
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Status: There are n pending request
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4 GB 0x0000 0000 0x6C00 0000 0x6CFF
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Device D2D OCM_ROM OCM_RAM ROM (32K
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Public Version www.ti.com On-Chip M
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