Chapter 10 Memory Subsystem.pdf

Public Version
www.ti.com SDRAM Controller (SDRC) Subsystem
Bits Field Name Description Type Reset
31:10 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x000000
9:8 CS1STARTLOW CS1 address space start address (lower add bits a1:a0) / 32MB unit RW 0x0
7:4 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
3:0 CS1STARTHIGH CS1 address space start address (upper add bits a5:a4:a3:a2) / 128MB RW 0x4
unit
Table 10-160. Register Call Summary for Register SDRC_CS_CFG
SDRAM Controller (SDRC) Subsystem
• CS0-CS1 Memory Spaces: [0] [1] [2] [3] [4]
• Chip-Select Configuration: [5] [6]
• CS Memory Spaces: [7] [8] [9] [10] [11] [12] [13]
• SDRC Register Summary: [14]
Address Offset 0x0000 0044
Table 10-161. SDRC_SHARING
Physical Address 0x6D00 0044 Instance SDRC
Description This register specifies the SDRC attached memory size and position on the SDRC IOs.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
LOCK
RESERVED RESERVED
Bits Field Name Description Type Reset
31 RESERVED Write 0s for future compatibility. RW 0x0
Read returns 0.
30 LOCK Read-only access lock bit RW See (1)
0x0: This register is fully writable.
0x1: When this bit is set, the register can not be unset until next reset
of the module.
29:15 RESERVED Write 0s for future compatibility. RW See (1)
Read returns 0s.
14:12 CS1MUXCFG Identifies the SDRC pins used by CS1 RW See (1)
0x0: 32-bit SDRAM on Datalane[31:0]
0x1: 32-bit SDRAM on Datalane[31:0]
0x2: 16-bit SDRAM on Datalane[31:16]
0x3: 16-bit SDRAM on Datalane[16:0]
0x4: Reserved
0x5: Reserved
0x6: Reserved
0x7: 16-bit SDRAM on Datalane[31:16]
(1) Reset value is copied from the system control module. See the note in Section 10.2.5.3.2 and Section 13.4.9, SDRC Registers, in
Chapter 13, System Control Module.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
CS1MUXCFG
CS0MUXCFG
Copyright © 2010–2011, Texas Instruments Incorporated
SDRCTRISTATE
2299