Chapter 10 Memory Subsystem.pdf

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B: Arbitration granularity Yes No No IDLE cycle mechanism: more than 2 idle cycles? Exclusive read? End of BURSTCOMPLETE transaction?* Use Rotation Engine? No No No Yes End of EXTENDEDGRANT transaction? Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Figure 10-75. Arbitration Granularity Yes Yes A Yes End of NOFSERVICES transaction? Allows the arbiter to wait for 1 idle cycle before moving the arbitration grant to another thread. A: Arbitration decision Atomic request: is a command inserted after RdEx and before its associated unlocking WNP? The priority can be given to a group within a class until the complete burst that is to proceed has been stored into the FIFO. A burst transaction should always be completed. * Only if BURSTCOMPLETE is active for the request which has access Per group, define the number of consecutive transactions this group can be granted. 2276 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 No Copyright © 2010–2011, Texas Instruments Incorporated B sdrc-032
4 GB 0x0000 0000 0x6C00 0000 0x6CFF FFFF 0x6D00 0000 0x6DFF FFFF 0x7000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xE000 0000 0xFFFF FFFF MPU global address space* SMS registers SDRC registers Virtual address space 0 (Q1) CS0 memory space CS1 memory space Virtual address space 1 (Q3) 256 MB 1 GB 512 MB * Internal physical address, from a SW point of vue Public Version www.ti.com SDRAM Controller (SDRC) Subsystem 10.2.6.3 Understanding SDRAM Subsystem Address Spaces 10.2.6.3.1 Physical vs Virtual Address Spaces One thing that the SMS does is to translate virtual addresses into physical SDRAM addresses in case of rotation only; that is, when accessing virtual address space 0 (quarter 1) and virtual address space 1 (quarter 3) as shown in Figure 10-76. The SMS then reinserts a request, or multiple requests depending on the SMS parameters, in the SMS request path to the SDRC (through the VRFB or not). The SDRAM subsytem global memory space mapping reaches 1.768G-bytes: • 1G-byte of CS memory space (CS0 and CS1 memory spaces): the SDRC automatically accesses the two external memory devices through direct accesses (addresses are simply translated). • 768M-bytes of virtual address space (address space 0 and address space 1): the SDRC automatically accesses the two external memory devices trough re-organized access (requests are modified accordingly to the context number and rotation angle before address translation). See section Section 10.2.6.3.1.2 for more information on VRFB contexts and rotation angles. Figure 10-76. SDRC Address Space in MPU Global Address Space Configuration register space is detailed in Table 10-108. SDRAM 0 (CS0) 256 MB SDRAM 1 (CS1) 512 MB Table 10-108. SDRC and SMS Configuration Register Space sdrc-037 Module Start Address End Address Total Space SMS 0x6C00 0000 0x6CFF FFFF 16 MB SDRC 0x6D00 0000 0x6DFF FFFF 16 MB 10.2.6.3.1.1 Physical Address Space The physical address space of the SDRC is 1G byte (maximum addressing capability). The SDRC has a memory device capacity of 16M bits to 2G bits. The smallest granularity of supported memory device is 16M bits/2M bytes. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2277
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Page 131 and 132: Level 0 Region 0 Public Version www
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Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
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Page 221 and 222: Public Version www.ti.com On-Chip M
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