Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Bits Field Name Description Type Reset 2 DDRTYPE DDR memory type (assuming RAMTYPE = 01) RW 0x- 0x0: Mobile DDR 0x1: Reserved for future use 1:0 RAMTYPE Memory type RW 0x- 0x0: SDR-SDRAM (single data rate) 0x1: DDR-SDRAM (double data rate) 0x2: Reserved 0x3: Reserved Table 10-175. SDRC_MR_p Address Offset 0x0000 0084 + (0x0000 0030 * p) Index p = 0 to 1 Physical Address 0x6D00 0084 + (0x0000 0030 * p) Instance SDRC Description This 12-bit register corresponds to the JEDEC SDRAM MR register, with the standard bit fields. All 12 bits are loaded into memory for future extension support. The SDRC keeps an internal copy register used internally; that is, returned when a read access is performed at that address. Load into memory on interconnect write access using MRS command with BA1,BA0 = 0,0. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CASL BL Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000 11:10 ZERO_1 Write 0s, as required by memory specifications. Read returns 0. RW 0x0 9 WBST Write burst support must be zero. RW 0x0 0x0: Write burst equals read burst 0x1: Write burst disable (single write access only) 8:7 ZERO_0 Write 0s, as required by memory specifications. Read returns 0s. RW 0x0 6:4 CASL CAS latency as defined by clock periods RW 0x2 0x1: CAS latency = 1 0x2: CAS latency = 2 0x3: CAS latency = 3 0x4: CAS latency = 4 0x5: CAS latency = 5 3 SIL Serial or interleaved mode: must be zero RW 0x0 0x0: Serial mode (always used) 0x1: interleaved mode (never used) 2:0 BL Memory burst length RW 0x4 0x0: Burst length = 1 - Not supported 0x1: Burst length = 2 - SDR memory only 0x2: Burst length = 4 - DDR memory only 0x3: Burst length = 8 - Not supported 0x4: Reserved 0x5: Reserved 0x6: Reserved 0x7: Full page - Not supported 2308 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 ZERO_1 Copyright © 2010–2011, Texas Instruments Incorporated WBST ZERO_0 SIL
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem Table 10-176. Register Call Summary for Register SDRC_MR_p SDRAM Controller (SDRC) Subsystem • SDRC Power-Down Mode: [0] • Mode Register (MR): [1] [2] [3] [4] [5] [6] • Mode Register Programming and Modes of Operation: [7] [8] [9] • Low-Power SDR/Mobile DDR Initialization Sequence: [10] • Read/Write Access: [11] • SDRC Register Summary: [12] • SDRC Register Description: [13] [14] Table 10-177. SDRC_EMR2_p Address Offset 0x0000 008C + (0x0000 0030 * p) Index p = 0 to 1 Physical Address 0x6D00 008C + (0x0000 0030 * p) Instance SDRC Description This 12-bit register corresponds to the low-power EMR register, as defined in the mobile DDR JEDEC Standard. All 12 bits are loaded into the memory, thus assuring future extension support. The SDRC keeps an internal copy register used internally; that is, returned when a read access is performed at that address. Load into memory on interconnect write access using MRS command with BA1,BA0 = 1,0. Type RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ZERO DS TCSR PASR Bits Field Name Description Type Reset 31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000 11:8 ZERO Write 0s, as required by memory specifications. Read returns 0 RW 0x00 7:5 DS Driver strength RW 0x0 0x0: Full strength driver 0x1: Half strength driver 0x2: Reserved 0x3: Reserved 0x4: Three-fourths strength driver (1) 0v5: Reserved 0x6: Optional one-fourth strength driver 0v7: Optional one-eighth strength driver 4:3 TCSR Temperature-compensated self-refresh RW 0x0 0x0: 70 degrees maximum temperature 0x1: 45 degrees maximum temperature 0x2: 15 degrees maximum temperature 0x3: 85 degrees maximum temperature 2:0 PASR Partial array self-refresh RW 0x0 0x0: All banks. 0x1: 1/2 array 0x2: 1/4 array 0x3: Reserved 0x4: Reserved 0x5: 1/8 array 0x6: 1/16 array 0x7: Reserved (1) Three-fourths strength driver is optional for speed bins LPDDR333 and below. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2309
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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BANKALLOCATION = 0b00 BANKALLOCATIO
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Endianism CSnMUXCFG field SDRC.SDRC
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CLK CMD WRITE DQ DQS CLK CMD DQ DQS
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CLK_IN SIGNAL_IN MODEMAXDELAY Initi
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Page 163 and 164: Public Version www.ti.com SDRAM Con
Page 167 and 168: 8 bits 32 bits Y0 U Y1 V P0 P1 16 b
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