Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
10.1.5.4.2 Wait Monitoring During an Asynchronous Write Access
When wait-pin monitoring is enabled for write accesses (GPMC.GPMC_CONFIG1_i[21]
WAITWRITEMONITORING bit = 0x1), the WAIT-invalid timing window is defined by the WRACCESSTIME
field. WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before
WRACCESSTIME completes. The advance pipelining of the two GPMC clock cycles is the result of the
internal synchronization requirements for the WAIT signal.
• WAIT monitored as active freezes the CYCLETIME counter. This informs the GPMC that the data bus
is not captured by the external device. The control signals are kept in their current state. The data bus
still drives the data.
• WAIT monitored as inactive unfreezes the CYCLETIME counter. This informs that the data bus is
correctly captured by the external device. All signals, including the data bus, are controlled according
to their related control timing value and to the CYCLETIME counter status.
When a delay larger than two GPMC clock cycles must be observed between wait-pin deassertion time
and the effective data write into the external device (including the required GPMC data setup time and the
device data setup time), an extra delay can be added between wait-pin deassertion time detection and
effective data write time into the external device and the effective unfreezing of the CYCLETIME counter.
This extra delay can be programmed in the GPMC.GPMC_CONFIG1_i[19:18] WAITMONITORINGTIME
fields (i = 0 to 7).
NOTE:
• The WAITMONITORINGTIME parameter does not delay the wait-pin assertion or
deassertion detection, nor does it modify the two GPMC clock cycles pipelined detection
delay.
• This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the
access is defined as synchronous, and even though no clock is provided to the external
device. Still, GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER is used as a divider for the
GPMC clock and so it must be programmed to define the correct
WAITMONITORINGTIME delay.
10.1.5.4.3 Wait Monitoring During a Synchronous Read Access
During synchronous accesses with wait-pin monitoring enabled, the wait pin is captured synchronously
with GPMC_CLK, using the rising edge of this clock.
The WAIT signal can be programmed to apply to the same clock cycle it is captured in. Alternatively, it can
be sampled one or two GPMC_CLK cycles ahead of the clock cycle it applies to. This pipelining is
applicable to the entire burst access, and to all data phase in the burst access. This WAIT pipelining depth
is programmed in the GPMC.GPMC_CONFIG1_i[19:18] WAITMONITORINGTIME field (where i = 0 to 7),
and is expressed as a number of GPMC_CLK clock cycles.
In synchronous mode, when wait-pin monitoring is enabled (GPMC.GPMC_CONFIG1_i[22]
WAITREADMONITORING bit), the effective access time is a logical AND combination of the
RDACCESSTIME timing completion and the WAIT deasserted-state detection.
Depending on the programmed WAITMONITORINGTIME value, the wait pin should be at a valid level,
either asserted or deasserted:
• In the same clock cycle the data is valid if WAITMONITORINGTIME = 0 ( at RDACCESSTIME
completion)
• In the WAITMONITORINGTIME * (GPMCFCLKDIVIDER + 1) GPMC_FCLK clock cycles before
RDACCESSTIME completion if WAITMONITORINGTIME =/ 0
Similarly, during a multiple-access cycle (burst mode), the effective access time is a logical AND
combination of PAGEBURSTACCESSTIME timing completion and the wait-inactive state. The Wait
pipelining depth programming applies to the whole burst access.
• WAIT monitored as active freezes the CYCLETIME counter. For an access within a burst (when the
CYCLETIME counter is by definition in a lock state), WAIT monitored as active extends the current
access time in the burst. Control signals are kept in their current state. The data bus is considered
invalid, and no data are captured during this clock cycle.
2118 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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