Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Figure 10-61. Natural Scan Order 400 The display buffer is the one created in the example sequence. When the application is running and uses the portrait orientation for the display (typically, a PDA-type application): • The DSS controller accesses the frame buffer using the 0-degree view. • The processor and other initiators, such as 2D DMA or 3D accelerators, use the 90-degree view. When the application is running and uses the landscape orientation for the display (typically, a video recorder/player or gaming application): • The DSS controller still accesses the frame buffer using the 0-degree view. • The processor and other initiators, such as 2D DMA or 3D accelerators, also use the 0-degree view. See Section 10.2.6.1.1. 10.2.5.1.3 Memory-Access Scheduler Configuration The memory-access scheduler is configured as follows: • For each of the three classes, the arbitration parameters are: 300 – SMS.SMS_CLASS_ARBITER0 through SMS.SMS_CLASS_ARBITER2 • One high-priority FIFO queue in the class (HIGHPRIOVECTOR field) • Number of consecutive transactions to perform (EXTENDEDGRANT field) • Burst transaction submitted for arbitration immediately or after the burst has been buffered (BURST-COMPLETE field) 10.2.5.1.4 Error Logging All data transfers in the SMS are full handshake. The SMS uses this capability to signal the system when a transaction error is detected. The SMS captures the address of the faulty access in the SMS.SMS_ERR_ADDR register. The error type is logged in the SMS.SMS_ERR_TYPE register. Once a faulty access is logged and the SMS.SMS_ERR_TYPE[0] ERRORVALID bit is set, the next faulty accesses cannot be logged before clearing the ERRORVALID bit. In the case of an interconnect transaction, an error response is generated if any of the following occur: • An incoming request arrives after an idle request from the PRCM. • An illegal command is received. • A protection region overlap is detected. • Protection errors. 2248 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated sdrc-018
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem It is assumed that the system interconnect on which the SMS is plugged is responsible for signaling the error event to the host MPU based on the interconnect response. The MPU error handler can then consult the error logging registers. 10.2.5.2 SDRC Configuration 10.2.5.2.1 IP Revision The IP revision code can be read in the SDRC.SDRC_REVISION[7:0] REV field. 10.2.5.2.2 Reset Behavior The reset behavior of the SDRC can be classified into three subgroups: • Asynchronous cold-reset (power-on reset) behavior • Asynchronous warm reset behavior • Synchronous soft-reset behavior When the system-wide power-on reset is applied through cold reset, all flops are reset to their default values, and all state-machines are returned to their idle states. The programming model for data recovery following a warm reset is as follows: • Program the SDRC.SDRC_POWER_REG register to enable the SDRC.SDRC_POWER_REG[7] SRFRONRESET bit. A warm reset condition is then issued. • The SDRC enters self-refresh mode since the SRFRONRESET bit is set. • The SDRC does not execute global SDRC reset since the reset is not qualified as cold. • The SDRC state-machine maintains the external memory device in self-refresh. The first SDRC access to the configuration register must then be: 1. Check the SDRC configuration. 2. Exit self-refresh mode using the manual command register. A software-controlled reset is also available by using the SDRC.SDRC_SYSCONFIG[1] SOFTRESET bit (set this bit to 1 to activate the reset). The completion of the reset can be determined by reading the SDRC.SDRC_SYSSTATUS[0] RESETDONE bit. When the SDRC is reset due to the presence of either a soft or cold reset, all SDRC flops are reset. NOTE: SDRC Requirement at First Power-Up to Have sdrc_cke Pin High To comply with the JEDEC standard, sdrc_cke pins values are forced to 1 during the initial memory power-up phase: software must ensure that sdrc_cke pin is released after the initialization phase; it happens only at first power-up (on a cold reset). Thus, at the end of the initial SDRC power-up sequence and before programing the PWDENA field, software must ensure that the sdrc_cke pin is driven by the SDRC module. Then the value of the PWDENA field can be modified. See Section 10.2.5.4.1 for more details on sdrc_cke driving. NOTE: Set the INPUTENABLE0 bit of CONTROL.CONTROL_PADCONF_SDRC_CLK to assure the synchronization of sdrc_clk. For more information, see Chapter 13, System Control Module. 10.2.5.3 SDRC Setup A number of device parameters must be set before executing the initialization sequence. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2249
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Device D2D OCM_ROM OCM_RAM ROM (32K
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