Chapter 10 Memory Subsystem.pdf

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SDRAM Controller (SDRC) Subsystem www.ti.com
• The out-of-band error signal generation using two out-of-band error signals
Based on the fact that there is no way to prevent the debugger from generating firewall violations during
debug, and that users cannot stop checking for functional violations, two out-of-band violation signals are
set when:
• A functional violation is detected
• A debug violation is detected
These signals are asserted on each error detection from a read, write, or posted write faulty access: they
are deasserted when the software clears the error bit in the SMS_ERR_TYPE register.
10.2.4.2 Module Power Saving
Power-saving is managed through the SMS.SMS_SYSCONFIG register.
The SMS_SYSCONFIG[4:3] SIDLEMODE field defines the power management strategy (force idle mode,
no idle mode, or smart idle mode). See Section 10.2.4.3 for more details about the system power
management.
By default, the internal interface clock gating strategy is enabled as the SMS_SYSCONFIG[0] AUTOIDLE
bit is set to 0x1 after reset. When all FIFO queues are empty and no ongoing transactions remain, the L3
interconnect clock is disabled inside the SMS thus reducing power consumption. The L3 interconnect
clock can be disabled after a programmable delay defined in the SMS_POW_CTRL[7:0] IDLEDELAY bit
field.
When there is new activity on the interconnect interface, the interconnect clock is restarted without any
latency penalty. It is recommended to enable this mode to reduce power consumption.
There is an internal interface clock gating strategy within the SDRC. This power-saving feature is always
active.
10.2.4.3 System Power Management
The SMS can be configured through the SMS.SMS_SYSCONFIG register to be in one of these idle
modes:
• No-idle mode (the SMS.SMS_SYSCONFIG[4:3] SIDLEMODE field is set to 0x1): The module never
goes into idle state.
• Force-idle mode (the SMS.SMS_SYSCONFIG[4:3] SIDLEMODE field is set to 0x0): The module goes
into idle state immediately after receiving the request from the PRCM.
• Smart-idle mode (the SMS.SMS_SYSCONFIG[4:3] SIDLEMODE field is set to 0x2): SidleAck is
asserted once the module has confirmed there are no more outstanding transactions with the SDRC.
10.2.4.4 SDRC
The SDRC provides two configurable memory areas. Each supports mobile SDR SDRAM and low-power
DDR SDRAM from 16 Mbits to 4 Gbits, depending on the memory organization.
Flexible row/column addressing schemes are possible with 2-bank support for 16 Mbits and 32 Mbits
memories, and 4-bank support for 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, 2 Gbits, and 4 Gbits
memories.
Figure 10-50 shows the architecture of the SDRC.
2228 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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