Chapter 10 Memory Subsystem.pdf

Public Version
www.ti.com General-Purpose Memory Controller
ADVEXTRADELAY must be used carefully to avoid control-signal overlap between successive accesses
to different chip-selects. This implies the need to program the RDCYCLETIME and WRCYCLETIME bit
fields to be greater than nADV/ALE signal-deassertion time, including the extra half-GPMC_FCLK-period
delay.
See Section 10.1.5.14 for more details about ADVONTIME, ADVRDOFFTIME, and ADVWROFFTIME use
for command (CLE) and address latch enable (ALE) use for a NAND flash interface.
10.1.5.3.4 nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time
(OEONTIME/OEOFFTIME/OEEXTRADELAY)
The GPMC.GPMC_CONFIG4_i[3:0] OEONTIME field (where i = 0 to 7) defines the nOE/nRE signal
assertion time relative to start access time. It is applicable only to read accesses.
The GPMC.GPMC_CONFIG4_i[12:8] OEOFFTIME field defines the nOE/nRE signal deassertion time
relative to start access time. It is applicable only to read accesses.
OEONTIME and OEOFFTIME parameters are applicable to synchronous and asynchronous modes.
OEONTIME can be used to control an address and byte enable valid setup time control before nOE/nRE
assertion. OEOFFTIME can be used to control an address and byte enable valid hold time control after
nOE/nRE assertion.
The nOE/RE signal transitions as controlled through OEONTIME, and OEOFFTIME can be delayed by
half a GPMC_FCLK period by enabling the GPMC.GPMC_CONFIG4_i[7] OEEXTRADELAY bit. This half
of a GPMC_FCLK period provides more granularity on nOE/RE assertion and deassertion time to
guaranty proper setup and hold time relative to GPMC_CLK. If asserted, OEEXTRADELAY applies to all
parameters controlling nOE/nRE transitions.
OEEXTRADELAY must be used carefully, to avoid control-signal overlap between successive accesses to
different chip-selects. This implies the need to program RDCYCLETIME and WRCYCLETIME to be
greater than nOE/RE signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
nOE/nRE is not asserted during a write cycle.
NOTE: When the GPMC generates a read access to an address-/data-multiplexed device, it drives
the address bus until nOE assertion time.
10.1.5.3.5 nWE: Write Enable Signal Control Assertion/Deassertion Time
(WEONTIME/WEOFFTIME/WEEXTRADELAY)
The GPMC.GPMC_CONFIG4_i[19:16] WEONTIME field (where i = 0 to 7) defines the nWE
signal-assertion time relative to start access time. It applies only to write accesses.
The GPMC.GPMC_CONFIG4_i[28:24] WEOFFTIME field defines the nWE signal-deassertion time relative
to start access time. It applies only to write accesses.
WEONTIME can be used to control an address and byte enable valid setup time control before nWE
assertion. WEOFFTIME can be used to control an address and byte enable valid hold time control after
nWE assertion.
nWE signal transitions as controlled through WEONTIME, and WEOFFTIME can be delayed by half a
GPMC_FCLK period by enabling the GPMC.GPMC_CONFIG4_i[23] WEEXTRADELAY bit. This half of a
GPMC_FCLK period provides more granularity on nWE assertion and deassertion time to guaranty proper
setup and hold time relative to GPMC_CLK. If asserted, WEEXTRADELAY applies to all parameters
controlling nWE transitions.
The WEEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the WRCYCLETIME bit field to be
greater than the nWE signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
nWE is not asserted during a read cycle.
SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem
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