Chapter 10 Memory Subsystem.pdf

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General-Purpose Memory Controller www.ti.com
10.1.5.3.6 GPMC_CLK
GPMC_CLK is the external clock provided to the attached synchronous memory or device.
• The GPMC_CLK clock frequency is the GPMC_FCLK functional clock frequency divided by 1, 2, 3, or
4, depending on the GPMC.GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER bit field (where i = 0 to 7),
with a guaranteed 50-percent duty cycle.
• The GPMC_CLK clock is only activated when the access in progress is defined as synchronous (read
or write access).
• The GPMC.GPMC_CONFIG1_i[26:25] CLKACTIVATIONTIME field (i = 0 to 7) defines the number of
GPMC_FCLK cycles from start access time to GPMC_CLK activation.
• The GPMC_CLK clock is stopped when cycle time completes and is asserted low between accesses.
• The GPMC_CLK clock is kept low when access is defined as asynchronous.
• When cycle time completes, the GPMC_CLK may be high because of the GPMCFCLKDIVIDER bit
field. To ensure correct stoppage of the GPMC_CLK clock within the 50-percent required duty cycle, it
is the user's responsibility to extend the RDCYCLETIME or WRCYCLETIME value.
• When the GPMC is configured for synchronous mode, the GPMC_CLK signal (which is an output)
must also be set as an input (CONTROL.CONTROL_PADCONF_GPMC_NCS7[24] INPUTENABLE1 =
1). GPMC_CLK is looped back through the output and input buffers of the corresponding GPMC_CLK
pad at the device boundary. The looped-back clock is used to synchronize the sampling of the memory
signals.
NOTE: To ensure a correct external clock cycle, the following rules must be applied:
• (RDCYCLETIME CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER +
1).
• The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER +
1).
10.1.5.3.7 GPMC_CLK and Control Signals Setup and Hold
Control-signal transition (assertion and deassertion) setup and hold values with respect to the GPMC_CLK
edge can be controlled in the following ways:
• For the GPMC_CLK signal, the GPMC.GPMC_CONFIG1_i[26:25] CLKACTIVATIONTIME field (i = 0 to
7) allows setup and hold control of control-signal assertion time.
• The use of a divided GPMC_CLK allows setup and hold control of control-signal assertion and
deassertion times.
• When GPMC_CLK runs at the GPMC_FCLK frequency so that GPMC_CLK edge and control-signal
transitions refer to the same GPMC_FCLK edge, the control-signal transitions can be delayed by half
of a GPMC_FCLK period to provide minimum setup and hold times. This half-GPMC_FCLK delay is
enabled with the CSEXTRADELAY, ADVEXTRADELAY, OEEXTRADELAY, or WEEXTRADELAY
parameter. This delay must be used carefully to prevent control-signal overlap between successive
accesses to different chip-selects. This implies that the RDCYCLETIME and WRCYCLETIME are
greater than the last control-signal deassertion time, including the extra half-GPMC_FCLK cycle.
10.1.5.3.8 Access Time (RDACCESSTIME / WRACCESSTIME)
The read access time and write access time durations can be programmed independently allowing nOE
and GPMC data capture timing parameters to be independent of nWE and memory device data capture
timing parameters.
RDACCESSTIME is programmed in the GPMC.GPMC_CONFIG5_i[20:16] bit field (i = 0 to 7).
WRACCESSTIME is programmed in the GPMC.GPMC_CONFIG6_i[28:24] bit field (i = 0 to 7).
RDACCESSTIME and WRACCESSTIME can be set from 0 to 31 GPMC_FCLK cycles with a granularity
of one (GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY = 0).
RDACCESSTIME and WRACCESSTIME can be set from 0 to 62 GPMC_FCLK cycles with a granularity
of two (GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY = 1).
2114 Memory Subsystem SPRUGN4L–May 2010–Revised June 2011
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