Chapter 10 Memory Subsystem.pdf

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Public Version SDRAM Controller (SDRC) Subsystem www.ti.com Table 10-110. SDRAM vs SDRC Characteristics SDRAM Parameter SDRC 512-Mbit MDDR SDRAM (16M * 32) Co mpa tibili ty Device type Mobile SDR / low-power DDR Low-power DDR yes Operating voltage VDD = VDDQ = 1.7V to 1.9V; VSS = VSSQ = 0.8xVDDQ >= High level
Public Version www.ti.com SDRAM Controller (SDRC) Subsystem 10.2.7 SMS Register Manual 10.2.7.1 SMS Instance Summary Table 10-111 describes the SMS module instance. Table 10-111. SMS Instance Summary Module Name Base Address Size SMS 0x6C00 0000 64K bytes 10.2.7.2 SMS Register Summary Table 10-112 summarizes the SMS register mapping summary. Table 10-112. SMS Register Summary Register Name Type Register Address Offset Physical Address Width (Bits) SMS_REVISION R 32 0x0000 0000 0x6C00 0000 SMS_SYSCONFIG RW 32 0x0000 0010 0x6C00 0010 SMS_SYSSTATUS R 32 0x0000 0014 0x6C00 0014 SMS_RG_ATTi (1) RW 32 0x0000 0048 + 0x6C00 0048 + (0x0000 0020 * i) (0x0000 0020 * i) SMS_RG_RDPERMi (1) RW 32 0x0000 0050 + 0x6C00 0050 + (0x0000 0020 * i) (0x0000 0020 * i) SMS_RG_WRPERMi (1) RW 32 0x0000 0058 + 0x6C00 0058 + (0x0000 0020 * i) (0x0000 0020 * i) SMS_RG_STARTj (2) RW 32 0x0000 0060 + 0x6C00 0060 + where k = j - 1 (3) (0x0000 0020 * k) (0x0000 0020 * k) SMS_RG_ENDj (2) RW 32 0x0000 0064 + 0x6C00 0064 + where k = j - 1 (3) (0x0000 0020 * k) (0x0000 0020 * k) SMS_CLASS_ARBITER0 RW 32 0x0000 0150 0x6C00 0150 SMS_CLASS_ARBITER1 RW 32 0x0000 0154 0x6C00 0154 SMS_CLASS_ARBITER2 RW 32 0x0000 0158 0x6C00 0158 SMS_INTERCLASS_ARBITER RW 32 0x0000 0160 0x6C00 0160 SMS_CLASS_ROTATIONm (4) RW 32 0x0000 0164 + 0x6C00 0164 + (0x0000 0004 * m) (0x0000 0004 * m) SMS_ERR_ADDR R 32 0x0000 0170 0x6C00 0170 SMS_ERR_TYPE RW 32 0x0000 0174 0x6C00 0174 SMS_POW_CTRL RW 32 0x0000 0178 0x6C00 0178 SMS_ROT_CONTROLn (5) RW 32 0x0000 0180 + 0x6C00 0180 + (0x0000 0010 * n) (0x0000 0010 * n) SMS_ROT_SIZEn (5) RW 32 0x0000 0184 + 0x6C00 0184 + (0x0000 0010 * n) (0x0000 0010 * n) SMS_ROT_PHYSICAL_BAn (5) RW 32 0x0000 0188 + 0x6C00 0188 + (0x0000 0010 * n) (0x0000 0010 * n) (1) i = 0 to 7 (2) j = 1 to 7 (3) k = 0 to 6 (4) m = 0 to 2 (5) n = 0 to 11 10.2.7.3 SMS Register Description This section provides a description of SMS registers. SPRUGN4L–May 2010–Revised June 2011 Memory Subsystem Copyright © 2010–2011, Texas Instruments Incorporated 2283
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This chapter describes the memory s
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Device GPMC External device/ memory
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Public Version www.ti.com General-P
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1 GBytes 512 MBytes 256 MBytes 128
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] (co
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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GPMC_FCLK GPMC_CLK gpmc_a[11:1] gpm
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nCS nBE0/CLE nWE nADV/ALE CSONTIME=
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nCS nBE0/CLE nWE Public Version www
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Row 0 Row 1 Row 2 Row 3 Row 252 Row
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512 Bytes input Row 0 Row 1 Row 2 R
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M0 Manual mode Rd/Wr/ SW Mode Size0
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M1 M2 M3 M4 Per-sector spares Spare
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M9 Per-sector spares, separate ECC
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GPMC_FCLK nCS nBE0/CLE nOE/nRE nADV
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Device GPMC module A [27:17] A [16:
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FCLK CLK nADV nCS nOE A/D bus ClkAc
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FCLK nCS nADV nWE A/D bus AdvWrOffT
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Public Version www.ti.com SDRAM Con
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Device SDRAM controller subsystem R
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MUX1 System address 31 30 29 28 27
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MUX23 System address Address mappin
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Configuration register file Rotatio
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Level 0 Region 0 Public Version www
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OCP slave interface OCP slave port
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Page 139 and 140: BANKALLOCATION = 0b00 BANKALLOCATIO
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Page 219 and 220: Device D2D OCM_ROM OCM_RAM ROM (32K
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